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| PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) PM5355 S/UNITM 622 S/UNI-622 SATURN USER NETWORK INTERFACE (622-MBIT/S) STANDARD PRODUCT DATA SHEET ISSUE 3: JUNE 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) PUBLIC REVISION HISTORY Issue No. 3 Issue Date June 1998 Details of Change Data Sheet Reformatted -- No Change in Technical Content. Generated R3 data sheet from PMC-930527, R8. 2 1 April 3, 1996 October 1994 Update to Eng Doc Issue 7 Creation of Document PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) CONTENTS 1 FEATURES ............................................................................................... 1 1.1 1.2 2 3 4 5 6 7 8 9 THE RECEIVER SECTION: .......................................................... 1 THE TRANSMITTER SECTION:.................................................... 2 APPLICATIONS ....................................................................................... 4 REFERENCES ......................................................................................... 5 APPLICATION EXAMPLES ...................................................................... 6 BLOCK DIAGRAM.................................................................................... 8 DESCRIPTION ....................................................................................... 10 PIN DIAGRAM ........................................................................................ 12 PIN DESCRIPTION ................................................................................ 13 FUNCTIONAL DESCRIPTION ............................................................... 29 9.1 RECEIVE SECTION OVERHEAD PROCESSOR........................ 29 9.1.1 FRAMER ........................................................................... 29 9.1.2 DESCRAMBLE ................................................................. 30 9.1.3 ERROR MONITOR............................................................ 30 9.1.4 LOSS OF SIGNAL ............................................................ 30 9.1.5 LOSS OF FRAME ............................................................. 30 9.2 RECEIVE LINE OVERHEAD PROCESSOR ............................... 31 9.2.1 LINE RDI DETECT............................................................ 31 9.2.2 LINE AIS DETECT ............................................................ 31 9.2.3 AUTOMATIC PROTECTION SWITCH CONTROL BLOCK31 9.2.4 ERROR MONITOR............................................................ 32 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.3 9.4 9.5 BYTE INTERLEAVED DEMULTIPLEXER.................................... 32 TRANSPORT OVERHEAD EXTRACT PORT.............................. 32 RECEIVE PATH OVERHEAD PROCESSOR ............................... 32 9.5.1 POINTER INTERPRETER ................................................ 33 9.5.2 SPE TIMING...................................................................... 38 9.5.3 ERROR MONITOR............................................................ 38 9.6 9.7 PATH OVERHEAD EXTRACT...................................................... 39 RECEIVE ATM CELL PROCESSOR ........................................... 39 9.7.1 CELL DELINEATION......................................................... 39 9.7.2 DESCRAMBLER............................................................... 40 9.7.3 CELL FILTER AND HCS VERIFICATION.......................... 40 9.7.4 PERFORMANCE MONITOR............................................. 42 9.7.5 GFC EXTRACTION PORT................................................ 42 9.7.6 RECEIVE FIFO ................................................................. 42 9.8 TRANSMIT SECTION OVERHEAD PROCESSOR ..................... 43 9.8.1 LINE AIS INSERT ............................................................. 43 9.8.2 BIP-8 INSERT ................................................................... 43 9.8.3 FRAMING AND IDENTITY INSERT.................................. 44 9.8.4 SCRAMBLER.................................................................... 44 9.9 TRANSMIT LINE OVERHEAD PROCESSOR ............................. 44 9.9.1 APS INSERT ..................................................................... 44 9.9.2 LINE BIP CALCULATE...................................................... 44 9.9.3 LINE RDI INSERT............................................................. 45 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.9.4 LINE FEBE INSERT.......................................................... 45 9.10 9.11 9.12 BYTE INTERLEAVED MULTIPLEXER ........................................ 45 TRANSPORT OVERHEAD INSERT PORT ................................. 45 TRANSMIT PATH OVERHEAD PROCESSOR ............................ 46 9.12.1 POINTER GENERATOR ................................................... 47 9.12.2 BIP-8 CALCULATE ........................................................... 48 9.12.3 FEBE CALCULATE ........................................................... 48 9.12.4 SPE MULTIPLEXER.......................................................... 48 9.13 9.14 PATH OVERHEAD INSERT ......................................................... 48 TRANSMIT ATM CELL PROCESSOR......................................... 50 9.14.1 IDLE/UNASSIGNED CELL GENERATOR......................... 50 9.14.2 SCRAMBLER.................................................................... 50 9.14.3 HCS GENERATOR............................................................ 50 9.14.4 GFC INSERTION PORT ................................................... 50 9.14.5 TRANSMIT FIFO............................................................... 51 9.15 SONET/SDH SECTION AND PATH TRACE BUFFERS............... 51 9.15.1 RECEIVE TRACE BUFFER (RTB) .................................... 51 9.15.2 TRANSMIT TRACE BUFFER (TTB).................................. 54 9.16 LINE SIDE INTERFACE............................................................... 54 9.16.1 RECEIVE INTERFACE...................................................... 54 9.16.2 TRANSMIT INTERFACE ................................................... 55 9.17 DROP SIDE INTERFACE ............................................................ 55 9.17.1 RECEIVE INTERFACE...................................................... 55 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.17.2 TRANSMIT INTERFACE ................................................... 56 9.18 9.19 9.20 9.21 10 11 PARALLEL I/O PORT................................................................... 56 JTAG TEST ACCESS PORT ........................................................ 56 MICROPROCESSOR INTERFACE ............................................. 56 REGISTER MEMORY MAP ......................................................... 56 NORMAL MODE REGISTER DESCRIPTION........................................ 62 TEST FEATURES DESCRIPTION ....................................................... 194 11.1 11.2 11.3 TEST MODE REGISTER MEMORY MAP ................................. 194 TEST MODE 0 DETAILS ........................................................... 199 JTAG TEST PORT...................................................................... 202 12 13 OPERATION ......................................................................................... 207 FUNCTIONAL TIMING ......................................................................... 223 13.1 13.2 13.3 13.4 13.5 13.6 LINE SIDE RECEIVE INTERFACE ............................................ 223 LINE SIDE TRANSMIT INTERFACE.......................................... 227 OVERHEAD ACCESS ............................................................... 229 GFC ACCESS............................................................................ 237 DROP SIDE RECEIVE INTERFACE.......................................... 238 DROP SIDE TRANSMIT INTERFACE ....................................... 241 14 15 16 17 18 ABSOLUTE MAXIMUM RATINGS........................................................ 242 D.C. CHARACTERISTICS .................................................................... 243 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 246 S/UNI-622 TIMING CHARACTERISTICS ............................................. 250 ORDERING AND THERMAL INFORMATION ...................................... 270 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 19 MECHANICAL INFORMATION............................................................. 271 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE v PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) LIST OF REGISTERS REGISTER 0X00: S/UNI-622 MASTER RESET AND IDENTITY / LOAD PERFORMANCE METERS.................................................................... 63 REGISTER 0X01: S/UNI-622 MASTER CONFIGURATION.............................. 64 REGISTER 0X02: S/UNI-622 MASTER INTERRUPT STATUS......................... 67 REGISTER 0X03: PISO INTERRUPT ............................................................... 69 REGISTER 0X04: S/UNI-622 MASTER CONTROL/MONITOR ........................ 70 REGISTER 0X05: S/UNI-622 MASTER AUTO ALARM .................................... 73 REGISTER 0X06: S/UNI-622 PARALLEL OUTPUT PORT ............................... 74 REGISTER 0X07: S/UNI-622 PARALLEL INPUT PORT................................... 75 REGISTER 0X08: S/UNI-622 PARALLEL INPUT PORT VALUE....................... 76 REGISTER 0X09: S/UNI-622 PARALLEL INPUT PORT ENABLE.................... 77 REGISTER 0X0A: S/UNI-622 TRANSMIT C1 ................................................... 78 REGISTER 0X0B: S/UNI-622 APS CONTROL/STATUS ................................... 79 REGISTER 0X0C: S/UNI-622 RECEIVE K1 ..................................................... 81 REGISTER 0X0D: S/UNI-622 RECEIVE K2 ..................................................... 82 REGISTER 0X0E: S/UNI-622 RECEIVE Z1...................................................... 83 REGISTER 0X0F: S/UNI-622 TRANSMIT Z1.................................................... 84 REGISTER 0X10: RSOP CONTROL/INTERRUPT ENABLE............................ 85 REGISTER 0X11: RSOP STATUS/INTERRUPT STATUS ................................. 87 REGISTER 0X12: RSOP SECTION BIP-8 LSB ................................................ 89 REGISTER 0X13: RSOP SECTION BIP-8 MSB ............................................... 90 REGISTER 0X14: TSOP CONTROL................................................................. 91 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE vi PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) REGISTER 0X15: TSOP DIAGNOSTIC ............................................................ 92 REGISTER 0X18: RLOP CONTROL/STATUS................................................... 93 REGISTER 0X19: RLOP INTERRUPT ENABLE/INTERRUPT STATUS ........... 95 REGISTER 0X1A: RLOP LINE BIP-96/24/8 LSB .............................................. 97 REGISTER 0X1B: RLOP LINE BIP-96/24/8...................................................... 98 REGISTER 0X1C: RLOP LINE BIP-96/24/8 MSB............................................. 99 REGISTER 0X1D: RLOP LINE FEBE LSB ..................................................... 100 REGISTER 0X1E: RLOP LINE FEBE ............................................................. 101 REGISTER 0X1F: RLOP LINE FEBE MSB..................................................... 102 REGISTER 0X20: TLOP CONTROL ............................................................... 103 REGISTER 0X21: TLOP DIAGNOSTIC .......................................................... 104 REGISTER 0X22: TLOP TRANSMIT K1 ......................................................... 105 REGISTER 0X23: TLOP TRANSMIT K2 ......................................................... 106 REGISTER 0X28 SSTB CONTROL................................................................ 107 REGISTER 0X29: SSTB SECTION TRACE IDENTIFIER STATUS................. 109 REGISTER 0X2A: SSTB INDIRECT ADDRESS REGISTER.......................... 111 REGISTER 0X2B: SSTB INDIRECT DATA REGISTER................................... 112 REGISTER 0X2C: SSTB EXPECTED CLOCK SYNCHRONIZATION MESSAGE .............................................................................................................. 113 REGISTER 0X2D: SSTB CLOCK SYNCHRONIZATION MESSAGE STATUS 114 REGISTER 0X30: RPOP STATUS/CONTROL ................................................ 116 REGISTER 0X31: RPOP INTERRUPT STATUS ............................................. 117 REGISTER 0X32: RPOP POINTER INTERRUPT STATUS ............................ 118 REGISTER 0X33: RPOP INTERRUPT ENABLE ............................................ 120 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE vii PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) REGISTER 0X34: RPOP POINTER INTERRUPT ENABLE ........................... 122 REGISTER 0X35: RPOP POINTER LSB ........................................................ 124 REGISTER 0X36: RPOP POINTER MSB ....................................................... 125 REGISTER 0X37: RPOP PATH SIGNAL LABEL............................................. 126 REGISTER 0X38: RPOP PATH BIP-8 LSB ..................................................... 127 REGISTER 0X39: RPOP PATH BIP-8 MSB .................................................... 128 REGISTER 0X3A: RPOP PATH FEBE LSB..................................................... 129 REGISTER 0X3B: RPOP PATH FEBE MSB.................................................... 130 REGISTER 0X3C: RPOP RDI ......................................................................... 131 REGISTER 0X3D: RPOP RING CONTROL.................................................... 132 REGISTER 0X40: TPOP CONTROL/DIAGNOSTIC........................................ 134 REGISTER 0X41: TPOP POINTER CONTROL .............................................. 136 REGISTER 0X43: TPOP CURRENT POINTER LSB ...................................... 139 REGISTER 0X44: TPOP CURRENT POINTER MSB ..................................... 140 REGISTER 0X45: TPOP ARBITRARY POINTER LSB ................................... 141 REGISTER 0X46: TPOP ARBITRARY POINTER MSB .................................. 142 REGISTER 0X47: TPOP PATH TRACE ........................................................... 143 REGISTER 0X48: TPOP PATH SIGNAL LABEL ............................................. 144 REGISTER 0X49: TPOP PATH STATUS.......................................................... 145 REGISTER 0X4A: TPOP PATH USER CHANNEL .......................................... 147 REGISTER 0X4B: TPOP PATH GROWTH #1 (Z3).......................................... 148 REGISTER 0X4C: TPOP PATH GROWTH #2 (Z4).......................................... 149 REGISTER 0X4D TPOP PATH GROWTH #3 (Z5) .......................................... 150 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE viii PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) REGISTER 0X50: RACP CONTROL............................................................... 151 REGISTER 0X51: RACP INTERRUPT STATUS.............................................. 153 REGISTER 0X52: RACP INTERRUPT ENABLE/CONTROL .......................... 155 REGISTER 0X53: RACP MATCH HEADER PATTERN ................................... 157 REGISTER 0X54: RACP MATCH HEADER MASK......................................... 158 REGISTER 0X55: RACP CORRECTABLE HCS ERROR COUNT (LSB) ....... 159 REGISTER 0X56: RACP CORRECTABLE HCS ERROR COUNT (MSB) ...... 160 REGISTER 0X57: RACP UNCORRECTABLE HCS ERROR COUNT (LSB) .. 161 REGISTER 0X58: RACP UNCORRECTABLE HCS ERROR COUNT (MSB) . 162 REGISTER 0X59: RACP RECEIVE CELL COUNTER (LSB) ......................... 163 REGISTER 0X5A: RACP RECEIVE CELL COUNTER ................................... 164 REGISTER 0X5B: RACP RECEIVE CELL COUNTER (MSB) ........................ 165 REGISTER 0X5C: GFC CONTROL/MISC. CONTROL ................................... 166 REGISTER 0X60: TACP CONTROL/STATUS.................................................. 168 REGISTER 0X61: TACP IDLE/UNASSIGNED CELL HEADER PATTERN ...... 170 REGISTER 0X62: TACP IDLE/UNASSIGNED CELL PAYLOAD OCTET PATTERN.............................................................................................. 171 REGISTER 0X63: TACP FIFO CONTROL....................................................... 172 REGISTER 0X64: TACP TRANSMIT CELL COUNTER (LSB) ........................ 174 REGISTER 0X65: TACP TRANSMIT CELL COUNTER .................................. 175 REGISTER 0X66: TACP TRANSMIT CELL COUNTER (MSB) ....................... 176 REGISTER 0X67: TACP FIXED STUFF / GFC ............................................... 177 REGISTER 0X68 SPTB CONTROL................................................................ 179 REGISTER 0X69: SPTB PATH TRACE IDENTIFIER STATUS ........................ 181 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ix PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) REGISTER 0X6A: SPTB INDIRECT ADDRESS REGISTER.......................... 183 REGISTER 0X6B: SPTB INDIRECT DATA REGISTER................................... 184 REGISTER 0X6C: SPTB EXPECTED PATH SIGNAL LABEL......................... 185 REGISTER 0X6D: SPTB PATH SIGNAL LABEL STATUS ............................... 186 REGISTER 0X70: BERM CONTROL .............................................................. 188 REGISTER 0X71: BERM INTERRUPT ........................................................... 189 REGISTER 0X72: BERM LINE BIP ACCUMULATION PERIOD LSB ............. 190 REGISTER 0X73: BERM LINE BIP ACCUMULATION PERIOD MSB ............ 191 REGISTER 0X74: BERM LINE BIP THRESHOLD LSB .................................. 192 REGISTER 0X75: BERM LINE BIP THRESHOLD MSB ................................. 193 REGISTER 0X80: MASTER TEST .................................................................. 198 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE x PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) LIST OF FIGURES FIGURE 1 - TYPICAL STS-12C/3C ATM INTERFACE ...................................... 6 FIGURE 2 - TYPICAL STS-1 ATM INTERFACE................................................. 7 FIGURE 3 - NORMAL OPERATING MODE....................................................... 8 FIGURE 4 - LOOPBACK MODES...................................................................... 9 FIGURE 5 - ...................................................................................................... 12 FIGURE 6 - POINTER INTERPRETATION STATE DIAGRAM ......................... 34 FIGURE 7 - ITU G.783 CONCATENATION INDICATOR STATE DIAGRAM.... 37 FIGURE 8 - ITU G.783 CONCATENATION INDICATOR IMPLEMENTATION . 38 FIGURE 9 - CELL DELINEATION STATE DIAGRAM....................................... 40 FIGURE 10- HCS VERIFICATION STATE DIAGRAM ....................................... 41 FIGURE 11- STS-12C (STM-4C) DEFAULT TRANSPORT OVERHEAD VALUES ....................................................................................................... 46 FIGURE 12- DEFAULT PATH OVERHEAD VALUES ......................................... 49 FIGURE 13- INPUT OBSERVATION CELL (IN_CELL) ................................... 204 FIGURE 14- OUTPUT CELL (OUT_CELL)..................................................... 205 FIGURE 15- BIDIRECTIONAL CELL (IO_CELL)............................................ 205 FIGURE 16- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 206 FIGURE 17- STS-1 MAPPING........................................................................ 207 FIGURE 18- STS-3C (STM-1) MAPPING ....................................................... 208 FIGURE 19- STS-12C (STM-4C) ATM MAPPING .......................................... 209 FIGURE 20-16- BIT WIDE, 27-WORD STRUCTURE ..................................... 214 FIGURE 21- BOUNDARY SCAN ARCHITECTURE........................................ 217 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE xi PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) FIGURE 22- TAP CONTROLLER FINITE STATE MACHINE .......................... 219 FIGURE 23- IN FRAME DECLARATION ........................................................ 223 FIGURE 24- OUT OF FRAME DECLARATION .............................................. 224 FIGURE 25- LOSS OF SIGNAL DECLARATION/REMOVAL.......................... 224 FIGURE 26- LOSS OF FRAME DECLARATION/REMOVAL .......................... 225 FIGURE 27- LINE AIS AND LINE RDI DECLARATION/REMOVAL ................ 225 FIGURE 28- LOSS OF POINTER DECLARATION/REMOVAL ....................... 226 FIGURE 29- PATH AIS DECLARATION/REMOVAL ........................................ 226 FIGURE 30- PATH REMOTE DEFECT INDICATION DECLARATION/REMOVAL ..................................................................................................... 227 FIGURE 31- STS-1 BIT-SERIAL TRANSMIT FRAME ALIGNMENT............... 227 FIGURE 32- STS-12C BYTE-SERIAL TRANSMIT FRAME ALIGNMENT ...... 228 FIGURE 33- STS-3C/1 BYTE-SERIAL TRANSMIT FRAME ALIGNMENT ..... 228 FIGURE 34- TRANSPORT OVERHEAD EXTRACTION................................. 229 FIGURE 35- TRANSPORT OVERHEAD ORDERWIRE AND USER CHANNEL EXTRACTION ................................................................................................. 230 FIGURE 36- TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA EXTRACTION ................................................................................................. 231 FIGURE 37- PATH OVERHEAD EXTRACTION .............................................. 232 FIGURE 38- TRANSPORT OVERHEAD INSERTION .................................... 233 FIGURE 39- TRANSPORT OVERHEAD ORDERWIRE AND USER CHANNEL INSERTION..................................................................................................... 234 FIGURE 40- TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA INSERTION..................................................................................................... 235 FIGURE 41- PATH OVERHEAD INSERTION.................................................. 236 FIGURE 42- GFC EXTRACTION PORT ......................................................... 237 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE xii PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) FIGURE 43- GFC INSERTION PORT............................................................. 238 FIGURE 44- RECEIVE SYNCHRONOUS FIFO, TSEN=0, RCALEVEL0=1 ... 238 FIGURE 45- RECEIVE SYNCHRONOUS FIFO, TSEN=0, RCALEVEL0=0 ... 239 FIGURE 46- RECEIVE SYNCHRONOUS FIFO, TSEN=1, RCALEVEL0=1 ... 240 FIGURE 47- TRANSMIT SYNCHRONOUS FIFO ........................................... 241 FIGURE 48- MICROPROCESSOR INTERFACE READ TIMING.................... 247 FIGURE 49- MICROPROCESSOR INTERFACE WRITE TIMING .................. 249 FIGURE 50- LINE SIDE RECEIVE INTERFACE TIMING ............................... 251 FIGURE 51- RECEIVE ALARM OUTPUT TIMING ......................................... 253 FIGURE 52- RECEIVE OVERHEAD ACCESS TIMING.................................. 255 FIGURE 53- RECEIVE GFC ACCESS TIMING .............................................. 257 FIGURE 54- LINE SIDE TRANSMIT INTERFACE TIMING............................. 258 FIGURE 55- TRANSMIT ALARM INPUT TIMING ........................................... 259 FIGURE 56- TRANSMIT OVERHEAD ACCESS TIMING................................ 261 FIGURE 57- TRANSMIT GFC ACCESS TIMING............................................ 264 FIGURE 58- DROP SIDE RECEIVE INTERFACE TIMING ............................. 265 FIGURE 59- DROP SIDE TRANSMIT INTERFACE........................................ 267 FIGURE 60- JTAG PORT INTERFACE TIMING.............................................. 268 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE xiii PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 - ...................................................................................................... 13 - ...................................................................................................... 53 - ...................................................................................................... 56 - ...................................................................................................... 64 - ...................................................................................................... 65 - .................................................................................................... 155 - .................................................................................................... 173 - .................................................................................................... 177 - .................................................................................................... 194 TABLE 10 - .................................................................................................... 199 TABLE 11 - .................................................................................................... 201 TABLE 12 - INSTRUCTION REGISTER........................................................ 202 TABLE 13 - .................................................................................................... 215 TABLE 14 - .................................................................................................... 215 TABLE 15 - .................................................................................................... 216 TABLE 16 - ABSOLUTE MAXIMUM RATINGS.............................................. 242 TABLE 17 - .................................................................................................... 243 TABLE 18 - MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 48) . ..................................................................................................... 246 TABLE 19 - MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 49) ..................................................................................................... 248 TABLE 20 - LINE SIDE RECEIVE INTERFACE (FIGURE 50)....................... 250 TABLE 21 - RECEIVE ALARM OUTPUT (FIGURE 51)................................. 251 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE xiv PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) TABLE 22 - RECEIVE OVERHEAD ACCESS (FIGURE 52) ......................... 254 TABLE 23 - RECEIVE OVERHEAD ACCESS (FIGURE 53) ......................... 256 TABLE 24 - LINE SIDE TRANSMIT INTERFACE (FIGURE 54) .................... 257 TABLE 25 - TRANSMIT ALARM INPUT (FIGURE 55) .................................. 258 TABLE 26 - TRANSMIT OVERHEAD ACCESS (FIGURE 56) ....................... 260 TABLE 27 - TRANSMIT GFC ACCESS (FIGURE 57) ................................... 263 TABLE 28 - DROP SIDE RECEIVE INTERFACE (FIGURE 58) .................... 264 TABLE 29 - DROP SIDE TRANSMIT INTERFACE (FIGURE 59) .................. 266 TABLE 30 - JTAG PORT INTERFACE (FIGURE 60) ..................................... 267 TABLE 31 - .................................................................................................... 270 TABLE 32 - .................................................................................................... 270 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE xv PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE xvi PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 1 FEATURES * Monolithic Saturn User Network Interface that implements the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432 and the ATM Forum BISDN Inter Carrier Interface (B-ICI) Specification. Supports a 77.76 Mbyte/s STS-12c (STM-4c), a 19.44 Mbyte/s STS-3c (STM-1), a 6.48 Mbyte/s STS-1, or a 51.84 Mbit/s STS-1 line side interface. Provides four-cell deep FIFO buffers in both the transmit and receive paths. Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. Provides a generic parallel output port and a generic parallel input port to control and monitor front end line devices. Provides a standard 5-signal P1149.1 JTAG test port for boundary scan board test purposes. Low-power, +5 Volt, CMOS technology. 208-pin high-performance plastic quad flat pack (PQFP) package. * * * * * * * 1.1 The receiver section: * * * Frames to and descrambles the received STS-12c/3c/1 (STM-4c/1, AU-3) stream. Filters and captures the automatic protection switch channel (APS) bytes in readable registers and detects APS byte failure. Interprets the received payload pointer (H1, H2) and extracts the STS-12c/3c/1 (STM-4c/1, AU-3) synchronous payload envelope and path overhead. Extracts ATM cells from the received STS-12c/3c/1 (STM-4c/1, AU-3) synchronous payload envelope using ATM cell delineation and provides optional ATM cell payload descrambling, header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering. Provides a generic 16-bit wide datapath interface to read extracted cells from an internal four-cell FIFO buffer. * * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) * * Extracts all transport overhead bytes and serializes them in four 5.184 Mbit/s streams for optional external processing. Extracts the section user channel (F1) and the order wire channels (E1, E2) and serializes them into three independent 64 kbit/s streams for optional external processing. Extracts the data communication channels (D1-D3, D4-D12) and serializes them at 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) for optional external processing. Extracts all path overhead bytes and serializes them at 576 kbit/s for optional external processing. Extracts the 16- or 64-byte section trace (C1) sequence and the 16- or 64byte path trace (J1) sequence into internal register banks. Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (AIS), path remote defect indication signal (RDI-P) and loss of cell delineation (LCD). Counts received section BIP-8 (B1) errors, received line BIP-96/24/8 (B2) errors, line far end block errors (line FEBEs), received path BIP-8 (B3) errors and path far end block errors (path FEBEs) for performance monitoring purposes. Counts received cells written into the receive FIFO, received HCS errored cells that are discarded, and received HCS errored cells that are corrected and passed on. Extracts and serializes the GFC field from all received cells (including idle/unassigned cells) for external processing. * * * * * * * 1.2 The transmitter section: * * * Provides an internal four-cell FIFO into which cells are written using a generic 16-bit wide datapath interface. Inserts the generic flow control (GFC) bits via a simple serial interface. Counts transmit cells read from the transmit FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) * * * * * * * Provides idle/unassigned cell insertion, HCS generation/insertion, and ATM cell payload scrambling. Inserts ATM cells into the transmitted STS-12c/3c/1 (STM-4c/1, AU-3) synchronous payload envelope. Inserts a register programmable path signal label. Generates the transmit payload pointer (H1, H2) and inserts the path overhead. Optionally inserts the 16- or 64-byte section trace (C1) sequence and the 16or 64-byte path trace (J1) sequence from internal register banks. Optionally inserts externally generated path overhead bytes received via a 576 kbit/s serial interface. Optionally inserts externally generated data communication channels (D1-D3, D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial stream. Optionally inserts externally generated section user channel (F1) and externally generated order wire channels (E1, E2) via three 64 kbit/s serial interfaces. Optionally inserts externally generated transport overhead bytes received via four 5.184 Mbit/s serial interfaces. Scrambles the transmitted STS-12c/3c/1 (STM-4c/1, AU-3) stream and inserts the framing bytes (A1, A2) and the identity byte (C1). Optionally inserts path alarm indication signal (AIS), path remote defect indication (RDI-P), line alarm indication signal (AIS) and line remote defect indication (LRDI) indication. Optionally inserts register programmable APS bytes. Inserts path BIP-8 codes (B3), path far end block error (FEBE) indications, line BIP-96/24/8 codes (B2), line far end block error (FEBE) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end. Allows forced insertion of all-zeros data (after scrambling), the corruption of the framing bytes or the corruption of the section, line, or path BIP-8 codes for diagnostic purposes. * * * * * * * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 2 APPLICATIONS * * * * * * Workstations LAN Switches and Hubs Routers Video Servers Backbones Broadband Switching Systems PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 3 REFERENCES 1. ITU-T Recommendation G.709 - "Synchronous Multiplexing Structure," Helsinki, March 1993. 2. ITU-T Recommendation I.432 - "B-ISDN User-Network Interface-Physical Interface Specification," Helsinki, March 1993. 3. Bell Communications Research - "SONET Transport Systems Common Generic Criteria", GR-253-CORE, Issue 1, December 1994. 4. Bell Communications Research - "Generic Requirements for Operations of Broadband Switching Systems", TA-NWT-00001248, Issue 2, October 1993. 5. ATM Forum - "622 Mbps Physical Layer Specification", af-phy-0046.000, January 1996. 6. ANSI T1.105-1991, Telecommunications - Digital Hierarchy - Optical Interface Rates and Formats Specifications (SONET) 7. IEEE 1149.1 - "Standard Test Access Port and Boundary Scan Architecture", May 21, 1990. 8. PMC-940212, ATM_SCI_PHY, "SATURN Compliant Interfaces For ATM Devices," October 1995, Issue 3. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 4 APPLICATION EXAMPLES The S/UNI-622 is typically used to implement the core of an ATM User Network Interface by which an ATM terminal is linked to an ATM switching system using SONET/SDH-compatible transport. The S/UNI-622 may find application at either end of terminal-to-switch links or switch-to-switch links, both in private network (LAN) and public network (WAN) situations. In a typical STS-3c (STM-1) or STS-12c (STM-4c) application, the S/UNI-622 requires a clock and data recovery/serial-to-parallel converter device in the receive direction and a serialto-parallel converter/clock synthesis device in the transmit direction on the line side. The clock synthesis function is not required if the transmit side is looptimed to the receive clock. The initial configuration and ongoing control and monitoring of the S/UNI-622 are normally provided via a generic microprocessor interface. The S/UNI-622 supports a "hardware-only" operating mode for STS-12c (STM-4c) where an external microprocessor is not required. This application is shown in Figure 1. Figure 1 - Typical STS-12c/3c ATM Interface Ref. Clock Clock Synthesis TCA TSD+/TCLK POUT[7:0] TRANSMIT OVERHEAD INSERT TRANSMIT ALARM INSERT SIGNALS E/O Parallel-toSerial & Serial to Parallel Converter TXPRTY[1:0] TDAT[15:0] TSOC TWRENB TRANSMIT CELL INTERFACE PM5355 S/UNI-622 SATURN USER NETWORK INTERFACE PICLK FPIN PIN[7:0] OOF TFCLK RCA RXPRTY[1:0] RDAT[15:0] RSOC RRDENB RFCLK RECEIVE CELL INTERFACE RSD+/- O/E Clock & Data Recovery RECEIVE OVERHEAD EXTRACT RECEIVE ALARM DETECT SIGNALS MICRO BUS FOR CONFIG, STATUS AND CONTROL In a typical STS-1 application, the S/UNI-622 requires a clock and data recovery device in the receive direction and a clock source in the transmit direction on the line side. The initial configuration and ongoing control and monitoring of the S/UNI-622 are normally provided via a generic microprocessor interface. A typical STS-1 ATM Interface is shown in Figure 2. On the receive side, an PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) external clock and data recovery device is used. On the transmit side, the S/UNI-622 is configured for looptime operation where the receive clock, RSICLK, is used as the transmit clock source. Figure 2 - Typical STS-1 ATM Interface TRANSMIT OVERHEAD INSERT TRANSMIT ALARM INSERT SIGNALS 51.84 MHz Reference E/O TCA TXPRTY[1:0] TSOUT TSICLK TDAT[15:0] TSOC TWRENB TRANSMIT CELL INTERFACE PM5355 S/UNI-622 SATURN USER NETWORK INTERFACE RSD TFCLK RCA RXPRTY[1:0] RDAT[15:0] RSOC RRDENB RFCLK O/E Clock & Data Recovery RSICLK RSIN RECEIVE CELL INTERFACE RECEIVE OVERHEAD EXTRACT RECEIVE ALARM DETECT SIGNALS MICRO BUS FOR CONFIG, STATUS AND CONTROL PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 5 BLOCK DIAGRAM Figure 3 TLAIS TSDCLK,TOWCLK TSD,TSOW,TSUC - Normal Operating Mode TLRDI TLDCLK TLD,TLOW TTOH[4:1] TTOHFP TTOHCLK TTOHEN TPOH TPOHFP TPOHCLK TPOHEN TCLK TFP GTOCLK POP[5:0] PIP[3:0] TSICLK TSOUT FPOUT POUT[7:0] OOF PICLK FPIN FPOS PIN[7:0] RSICLK RSIN L ine Side I/F Tx Section O/H Processor Section Trace Buffer Rx Section O/H Processor Transport O/H Insert Path O/H Insert Parallel Input/Output Port TDO TDI TCK TMS TRSTB JTAG Test Access Port TSOC TDAT[15:0] TXPRTY[1:0] TCA TWRENB TFCLK RSOC RDAT[15:0] RXPRTY[1:0] RCA RRDENB RFCLK Drop Side I/F RCP RGFC TSEN TPAIS TPRDI Tx Line O/H Processor Byte Interleaved Mux Tx Path O/H Processor Tx ConCat Processor Rx ConCat Processor Rx Path O/H Processor Tx ATM Cell Processor Path Trace Buffer Rx ATM Cell Processor Rx Line O/H Processor Byte Interleaved Demux Transport O/H Extract Path O/H Extract Microprocessor I/F LAIS LRDI RLDCLK RLD,RLOW RPOH RPOHFP RPOHCLK RTOH[4:1] RTOHFP RTOHCLK OHFP GROCLK LOS LOF RSDCLK,ROWCLK RSD,RSOW,RSUC PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE D[7:0] A[7:0] ALE CSB WRB RDB RSTB INTB LOP PAIS PRDI LCD TCP TGFC XOFF Tx ATM 4 Cell FIFO Rx ATM 4 Cell FIFO 8 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 4 - Loopback Modes Transport O/H Insert Tx Section O/H Processor L ine STS-1 Side LINE LOOPBACK I/F Section STS-1 Trace DIAGNOSTIC Buffer LOOPBACK Rx Section O/H Processor Path O/H Insert Parallel Input/Output Port JTAG Test Access Port Tx Line O/H Processor Byte Interleaved Mux Tx Path O/H Processor Tx ConCat Processor DIAGNOSTIC Path Trace PATH Rx ConCat LOOPBACK Buffer Processor Rx Path O/H Processor Tx ATM Cell Processor Tx ATM 4 Cell FIFO Drop Side I/F Rx Line O/H Processor Byte Interleaved Demux Rx ATM Cell Processor Rx ATM 4 Cell FIFO Transport O/H Extract Path O/H Extract Microprocessor I/F PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 6 DESCRIPTION The PM5355 S/UNI-622 SATURN User Network Interface is a monolithic integrated circuit that implements the SONET/SDH processing and ATM mapping functions of a 622-Mbit/s ATM User Network Interface. The S/UNI-622 receives SONET/SDH frames via a byte-serial interface (or bitserial interface for STS-1), and processes section, line, and path overhead. It performs framing (A1, A2), performs descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (Z2, G1) are also accumulated. The S/UNI-622 interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload. In addition to basic processing of the received SONET/SDH overhead, the S/UNI-622 provides convenient access to all overhead bytes, which are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired. The S/UNI-622 frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. The ATM cells that are passed are written to a four-cell FIFO buffer. The received cells are read from the FIFO using a generic 16-bit wide datapath interface. Counts of errored received ATM cell headers that are uncorrectable and those that are correctable are accumulated independently for performance monitoring purposes. The S/UNI-622 transmits SONET/SDH frames via a byte-serial interface (or bitserial interface for STS-1) and formats section, line, and path overhead appropriately. It performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (Z2, G1) are also inserted. The S/UNI-622 generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell payload. In addition to the basic formatting of the transmitted SONET/SDH overhead, the S/UNI-622 provides convenient access to all overhead bytes, which are optionally inserted from lower rate serial interfaces, allowing external sourcing of overhead, if desired. The S/UNI-622 also supports the insertion of a large variety of errors into the transmit stream, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications. ATM cells are written to an internal four-cell FIFO using a generic 16-bit wide datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. Generic flow control (GFC) bits may be inserted downstream of the FIFO via a serial link so that all FIFO latency may be bypassed. The S/UNI-622 provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed. No auxiliary clocks are required directly by the S/UNI-622 since it operates from two line clocks. The S/UNI-622 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-622 also provides a standard 5-signal P1149.1 JTAG test port for boundary scan board test purposes. The S/UNI-622 is implemented in low-power, +5 Volt, CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 208-pin PQFP package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 7 PIN DIAGRAM The S/UNI-622 is packaged in a 208-pin slugged plastic QFP package having a body size of 28 mm by 28 mm and a pin pitch of 0.5 mm. Figure 5 P IN 2 08 P IN 157 P IN 156 RT O H[1] RT O H[2] RT O H[3] RT O H[4] VD D_AC VSS _AC FPO S FPIN PIN[0] PIN[1] PIN[2] PIN[3] PIN[4] PIN[5] PIN[6] PIN[7] RS IN RS IC LK VD D_D C PICLK VSS _DC PO P[0] PO P[1] PO P[2] PO P[3] PO P[4] PO P[5] VD D_D C VSS _DC T DI TMS T RS T B T SO UT FPO UT PO UT [0] PO UT [1] VD D_AC VD D_D C VSS _DC VSS _AC PO UT [2] PO UT [3] PO UT [4] PO UT [5] PO UT [6] PO UT [7] VD D_D C VSS _DC PIP[0] PIP[1] PIP[2] PIP[3] P IN 1 RD AT [7] RD AT [8] RD AT [9] RD AT [10] RD AT [11] RD AT [12] RD AT [13] RD AT [14] RD AT [15] VD D_AC VD D_D C VSS _DC VSS _AC ALE A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] D[0] D[1] D[2] D[3] VD D_AC VD D_D C VSS _DC VSS _AC D[4] D[5] D[6] D[7] RS T B CS B W RB RD B IN T B VD D_D C VSS _DC T DA T [0] T DA T [1] T DA T [2] T DA T [3] T DA T [4] T DA T [5] T DA T [6] T DA T [7] T DA T [8] T DA T [9] T DA T [10] Index VSS _AC VSS _DC VD D_D C VD D_AC RD AT [6] RD AT [5] RD AT [4] RD AT [3] RD AT [2] RD AT [1] RD AT [0] RXPR T Y[1] RXPR T Y[0] RS O C RC A RG FC T SEN VSS _DC RF CLK VD D_D C LCD RC P RR DE NB PR DI VSS _AC VD D_AC PAIS RP O H VSS _DC VD D_D C LO P RP O H FP RP O H CLK O H FP G R O C LK RLD CLK RLD LAIS LRD I LO S RO W CLK RLO W VSS _DC VD D_D C OOF LO F RS O W RS UC RS D RS DC LK RT O HF P RT O HC LK P M 53 55 S /U N I-622 P IN 52 P IN 105 P IN 53 T DA T [11] T DA T [12] T DA T [13] T DA T [14] T DA T [15] T XPRT Y[0] T XPRT Y[1] T SO C T W RENB TGFC XO F F VSS _DC T FC LK VD D_D C T CA T CP BU S8 T CK T DO T PR DI T PAIS T FP T PO HC LK T PO HFP T PO HEN VSS _AC VSS _DC VD D_D C VD D_AC T PO H T T O H [4] T T O H [3] T T O H [2] T T O H [1] G T O CLK T LAIS T LRD I T LDC LK T LD TLOW T SU C TSOW T O W CLK VSS _DC T CLK VD D_D C T T O H CLK T T OHF P T T O H EN T SD CLK T SD T SICLK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 P IN 104 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 8 PIN DESCRIPTION Table 1 Pin Name Type Pin No. Function PICLK Input 137 The parallel input clock (PICLK) provides timing for S/UNI-622 receive function operation. PICLK is a 6.48 MHz (STS-1), 19.44 MHz (STS-3c/STM-1), or 77.76 MHz (STS-12c/STM-4c), nominally 50% duty cycle clock, depending on the selected operating mode. PIN[7:0] and FPIN are sampled on the rising edge of PICLK. RX_VCLK The test vector clock (RX_VCLK) signal is used during S/UNI-622 production testing to verify internal functionality. PIN[0] PIN[1] PIN[2] PIN[3] PIN[4] PIN[5] PIN[6] PIN[7] FPIN Input 148 147 146 145 144 143 142 141 The data input (PIN[7:0]) bus carries the byte-serial STS-12c/3c/1 stream. PIN[7:0] is sampled on the rising edge of PICLK. PIN[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit received). PIN[0] is the least significant bit (corresponding to bit 8 of each word, the last bit received). Input 149 The active-high framing position input (FPIN) signal indicates the SONET frame position on the PIN[7:0] bus. The byte position indicated by FPIN is selected by the FPOS input as described below. FPIN is sampled on the rising edge of PICLK. FPOS Input 150 The frame position input (FPOS) selects the frame byte position in the SONET frame indicated by the FPIN input. When FPOS is tied high and STS-3c or STS-12c mode is selected, a pulse on FPIN marks the third A2 framing byte position on the PIN[7:0] bus. When FPOS is tied low and STS-3c or STS-12c mode is selected, a pulse on FPIN marks the first synchronous payload envelope byte position after the C1 bytes on PIN[7:0]. When configured for STS-1 mode, a pulse on FPIN always marks the first synchronous payload envelope byte position after the C1 byte on PIN[7:0]. RSICLK Input 139 The receive serial incoming clock (RSICLK) provides timing for processing the bitserial STS-1 receive stream, RSIN. RSICLK is nominally a 51.84 MHz, 50% duty cycle clock. RSIN is sampled on the rising edge of RSICLK. RSICLK is divided by eight to produce GROCLK when the bit-serial STS-1 mode is selected. RSICLK should be disabled when the bit-serial STS-1 interface is not used. RSIN Input 140 The receive incoming serial stream (RSIN) carries the scrambled STS-1 stream in bit-serial format. RSIN is sampled on the rising edge of RSICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function OOF Output 164 The out of frame (OOF) signal is high while the S/UNI-622 is out of frame. OOF is low while the S/UNI-622 is in-frame. An out of frame declaration occurs when four consecutive errored framing patterns (A1 and A2 bytes) have been received. OOF is intended to be used to enable an upstream framing pattern detector to search for the framing pattern. This alarm indication is also available via register access. OOF is updated on the rising edge of PICLK. GROCLK Output 174 The generated receive outgoing clock (GROCLK) is nominally a 6.48 MHz or 19.44 MHz, 50% duty cycle clock. When configured for STS-1 bit-serial mode, GROCLK is the RSICLK clock input divided down by eight. For this mode, GROCLK is updated on the rising edge of RSICLK and is expected to be used to drive input PICLK. When configured for STS-1 or STS-3c byte-serial mode, GROCLK is a flowed through version of PICLK. When configured for STS-12c byte-serial mode, GROCLK is the PICLK clock input divided by four. For this mode, GROCLK is updated on the rising edge of PICLK. TCLK Input 97 The transmit clock (TCLK) provides timing for S/UNI-622 transmit function operation. TCLK should be a 6.48 MHz (STS-1), 19.44 MHz (STS-3c/STM-1), or 77.76 MHz (STS-12c/STM-4c), nominally 50% duty cycle clock, depending on the selected operating mode. TX_VCLK The test vector clock (TX_VCLK) signal is used during S/UNI-622 production testing to verify internal functionality. TFP Input 74 The active high transmit frame pulse (TFP) signal is used to align the SONET/SDH transport frame generated by the S/UNI-622 device to a system reference. TFP should be brought high for a single GTOCLK period every 810 (STS-1), 2430 (STS-3c), 2430 (STS-12c) GTOCLK cycles, or a multiple thereof. TFP may be tied low if such synchronization is not required. The offset between a pulse applied to the TFP input and the resultant FPOUT pulse is 18 TCLK periods in STS-1 mode, 26 TCLK periods in STS-3c mode and 81 TCLK periods in STS-12c mode. TFP is sampled on the rising edge of GTOCLK. POUT[0] POUT[1] POUT[2] POUT[3] POUT[4] POUT[5] POUT[6] POUT[7] Output 122 121 116 115 114 113 112 111 The parallel outgoing stream, (POUT[7:0]), carries the scrambled STS-12/3c/1 stream in byte-serial format. POUT[7:0] is updated on the rising edge of TCLK. POUT[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). POUT[0] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function FPOUT Output 123 The active-high framing position output (FPOUT) signal marks the frame alignment on the POUT[7:0] bus. FPOUT goes high for a single TCLK period during the first synchronous payload envelope byte after the twelve C1 bytes. FPOUT is updated on the rising edge of TCLK. TSICLK Input 104 The transmit serial incoming clock (TSICLK) provides timing for updating the bitserial outgoing stream when bit-serial STS-1 mode is selected. TSICLK is nominally a 51.84 MHz, 50% duty cycle clock. TSOUT is updated on the rising edge of TSICLK. TSICLK should be disabled when the bit-serial STS-1 interface is not used. TSOUT Output 124 The transmit serial outgoing stream, (TSOUT), carries the scrambled stream in bitserial format when STS-1 bit-serial mode is selected. TSOUT is updated on the rising edge of TSICLK. In STS-1 bit-serial mode with line loopback or loop time modes enabled, TSOUT is updated on the rising edge of RSICLK. GTOCLK Output 87 The generated transmit output clock (GTOCLK) is nominally a 6.48 MHz or 19.44 MHz, 50% duty cycle clock. When configured for STS-1 bit-serial mode, GTOCLK is the TSICLK clock input divided down by eight. For this mode, GTOCLK is updated on the rising edge of TSICLK and is expected to be used to drive input TCLK. In STS-1 bit-serial mode with line loopback or loop time modes enabled, GTOCLK is the RSICLK clock input divided down by eight and is updated on the rising edge of RSICLK. When configured for STS-1 or STS-3c byte-serial mode, GTOCLK is a flowed through version of TCLK. When configured for STS-12c byte-serial mode, GTOCLK is the TCLK clock input divided by four. For this mode, GTOCLK is updated on the rising edge of TCLK. LOS Output 169 The loss of signal (LOS) signal is set high when loss of signal is declared. This occurs when a violating period (20 3 s) of consecutive all-zeros bytes is detected on the incoming STS-12c/3c/1 signal (before descrambling). LOS is removed when two valid framing words (A1, A2) are detected and during the intervening time, no violating period of consecutive all zeros patterns is detected. This alarm indication is also available via register access. LOS is updated on the rising edge of PICLK. LOF Output 163 The loss of frame (LOF) signal is set high when loss of frame is declared. This occurs when an out-of-frame condition (as indicated by a high level on the OOF output) persists for a period of 3 ms. LOF is removed when an in-frame condition (as indicated by a low level on the OOF output) persists for a period of 3 ms. This alarm indication is also available via register access. LOF is updated on the rising edge of PICLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function LAIS Output 171 The line alarm indication signal (LAIS) is set high when line AIS is declared. This occurs when a 111 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for three or five consecutive frames as programmed using the RLOP Control/Status register. LAIS is removed when any pattern other than 111 is detected in bits 6, 7 and 8 of the K2 byte for three or five consecutive frames as programmed using the RLOP Control/Status register. This alarm indication is also available via register access. LAIS is updated on the rising edge of PICLK. LRDI Output 170 The line remote defect indication (LRDI) signal is set high when line RDI is declared. This occurs when a 110 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for three or five consecutive frames as programmed using the RLOP Control/Status register. LRDI is removed when any pattern other than 110 is detected in bits 6, 7 and 8 of the K2 byte for three or five consecutive frames as programmed using the RLOP Control/Status register. This alarm indication is also available via register access. LRDI is updated on the rising edge of PICLK. LOP Output 178 The loss of pointer (LOP) signal is set high when loss of pointer is declared. This occurs when a valid pointer (H1, H2) is not found in eight consecutive frames, or if eight consecutive new data flags are detected. LOP is removed when the same valid and normal pointer with a normal new data flag is detected in three consecutive frames. The loss of pointer state is not entered if the incoming stream contains path AIS. This alarm indication is also available via register access. LOP is updated on the falling edge of GROCLK. PAIS Output 182 The path AIS (PAIS) signal is set high when STS-path AIS is declared. This occurs when an all-ones pattern is observed in the pointer bytes (H1, H2) for three consecutive frames. Path AIS is removed when the same valid and normal pointer is detected for three consecutive frames or a legal pointer with an active NDF is received. This alarm indication is also available via register access. PAIS is updated on the falling edge of GROCLK. PRDI Output 185 The path remote defect indication (PRDI) signal is set high when a path remote defect indication is detected. This occurs when bit 5 of the path status byte (G1) is set high for five (or ten) consecutive frames. Path remote defect is removed when bit 5 of the G1 byte is set low for five (or ten) consecutive frames. This indication is also available via register access. PRDI is updated on the falling edge of GROCLK. LCD Output 188 The loss of cell delineation (LCD) signal indicates when cell delineation can not be found. LCD transitions high when an out of cell delineation (OCD) anomaly has persisted for 4 ms. Once asserted, LCD remains high until no OCD anomaly has been detected for 4 ms at which time, LCD is set low. The OCD state is entered when the cell delineation state machine is not in the SYNC state. Please refer to the Functional Description section for an explanation of the cell delineation state machine. This alarm indication is also available via register access. LCD is updated on the falling edge of GROCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function TLAIS Input 88 The active-high transmit line alarm indication (TLAIS) signal controls the insertion of line AIS. Line AIS is inserted by overwriting the SONET/SDH frame contents with all ones (before scrambling). The section overhead is not overwritten. This function can also be performed via register access. Line AIS insertion is internally synchronized to frame boundaries. The TLAIS input take precedence over the TTOH and TTOHEN inputs. TLAIS is sampled on the rising edge of TCLK. TLRDI Input 89 The active-high transmit line remote defect indication (TLRDI) signal controls the insertion of line RDI. Line RDI is inserted by transmitting the code 110 (binary) in bit positions 6,7, and 8 of the K2 byte. This function can also be performed via register access, or be enabled to occur automatically upon detection of receive line AIS, loss of signal, or loss of frame. The TLRDI input takes precedence over the TTOH and TTOHEN inputs. TLRDI is sampled on the rising edge of TCLK. TPAIS Input 73 The active-high transmit path alarm indication (TPAIS) signal controls the insertion of STS-path AIS. A high level on TPAIS forces the insertion of an all ones pattern into the complete synchronous payload envelope, and the payload pointer bytes (H1, H2). Path AIS insertion is internally synchronized to SPE frame boundaries. This function can also be performed via register access. TPAIS is sampled on the rising edge of GTOCLK. TPRDI Input 72 The transmit path remote defect indication (TPRDI) signal controls the insertion of the path remote defect indication signal. A high level on TPRDI forces a logic one to be inserted in the path remote defect indication bit position in the path status byte (G1). This function can also be performed via register access, or be enabled to occur automatically upon detection of receive line AIS, loss of frame, loss of signal, loss of pointer or path AIS. The TPOH and TPOHEN inputs take precedence over the TPRDI input. TPRDI is sampled on the rising edge of GTOCLK. RFCLK Input 190 The receive FIFO clock (RFCLK) is used to read words from the synchronous FIFO interface. RFCLK must cycle at a 52 MHz or lower rate, but at a high enough rate to avoid FIFO overflow. RRDENB is sampled using the rising edge of RFCLK. RSOC, RCA, RXPRTY[1:0] and RDAT[15:0] are updated on the rising edge of RFCLK. RRDENB Input 186 The active-low receive read enable input (RRDENB) is used to initiate reads from the receive FIFO. When sampled low using the rising edge of RFCLK, a word is read from the internal synchronous FIFO and output on bus RDAT[15:0]. When sampled high using the rising edge of RFCLK, no read is performed and outputs RDAT[15:0], RXPRTY[1:0] and RSOC are tristated if the TSEN input is high. RRDENB must operate in conjunction with RFCLK to access the FIFO at an instantaneous rate high enough to avoid FIFO overflows. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RXPRTY[0] RXPRTY[1] Tristate 198 199 200 201 202 203 204 1 2 3 4 5 6 7 8 9 The receive cell data (RDAT[15:0]) bus carries the ATM cell octets that are read from the receive FIFO. RDAT[15:0] is updated on the rising edge of RFCLK. When the S/UNI-622 is configured for tristate operation using the TSEN input, tristating of output bus RDAT[15:0] is controlled by input RRDENB. Tristate 196 197 The receive parity (RXPRTY[1:0]) signals indicate the parity of the RDAT[15:0] bus. In word parity mode, RXPRTY[1] is the parity calculation over the RDAT[15:0] bus and RXPRTY[0] is unused. In byte parity mode, RXPRTY[1] is the parity calculation over the RDAT[15:8] bus and RXPRTY[0] is the parity calculation over the RDAT[7:0] bus. Selection between word parity mode and byte parity mode is made using a register bit. Odd or even parity selection is made using a register bit. RXPRTY[1:0] is updated on the rising edge of RFCLK. When the S/UNI-622 is configured for tristate operation using the TSEN input, tristating of output bus RXPRTY[1:0] is control by input RRDENB. RSOC Tristate 195 The receive start of cell (RSOC) signal marks the start of cell on the RDAT[15:0] bus. When RSOC is high, the first word of the cell structure is present on the RDAT bus. RSOC is updated on the rising edge of RFCLK. When the S/UNI-622 is configured for tristate operation using the TSEN input, tristating of output RSOC is control by input RRDENB. RCA Output 194 The receive cell available (RCA) signal indicates when a cell is available in the receive FIFO. When high, RCA indicates that the receive FIFO has at least one cell available to be read. When RCA goes low, the receive FIFO contains only four words or is empty. Selection is made using a bit in the RACP Interrupt Enable/Control register. RCA is updated on the rising edge of RFCLK. The active polarity of TCA is programmable and defaults to active-high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function TSEN Input 192 The tristate enable (TSEN) signal allows tristate control over outputs RDAT[15:0], RXPRTY[1:0] and RSOC. When TSEN is high, the active-low receive read enable input, RRBENB, controls when outputs RDAT[15:0], RXPRTY[1:0] and RSOC are driven. When TSEN is low, outputs RDAT[15:0], RXPRTY[1:0] and RSOC are always driven. TFCLK Input 65 The transmit FIFO clock (TFCLK) is used to write words to the synchronous FIFO interface. TFCLK must cycle at a 52 MHz or lower rate. TWRENB, TSOC, TXPRTY[1:0] and TDAT[15:0] are sampled on the rising edge of TFCLK. In addition, TCA is updated on the rising edge of TFCLK. TWRENB Input 61 The active-low transmit write enable input (TWRENB) is used to initiate writes to the transmit FIFO. When sampled low using the rising edge of TFCLK, the 16-bit word on TDAT[15:0] is written into the transmit FIFO. When sampled high using the rising edge of TFCLK, no write is performed. A complete 53-octet cell must be written to the FIFO before it is inserted into the STS-12c/3c/1 SPE. Idle/unassigned cells are inserted when a complete cell is not available from the FIFO. TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] Input 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 The transmit cell data (TDAT[15:0]) bus carries the ATM cell octets that are written to the transmit FIFO. TDAT[15:0] is sampled on the rising edge of TFCLK and is considered valid only when TWRENB is simultaneously asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function TXPRTY[0] TXPRTY[1] Input 58 59 The transmit parity (TXPRTY[1:0]) signals indicate the parity of the TDAT[15:0] bus. In word parity mode, TXPRTY[1] is expected to be the parity calculation over the TDAT[15:0] bus and TXPRTY[0] is ignored. In byte parity mode, TXPRTY[1] is expected to be the parity calculation over the TDAT[15:8] bus and TXPRTY[0] is expected to be the parity calculation over the TDAT[7:0] bus. Selection between word parity mode and byte parity mode is made using a register bit. Odd or even parity selection is made using a register bit. TXPRTY[1:0] is sampled on the rising edge of TFCLK and is considered valid only when TWRENB is simultaneously asserted. TSOC Input 60 The transmit start of cell (TSOC) signal marks the start of cell on the TDAT[15:0] bus. When TSOC is high, the first word of the cell structure is present on the TDAT[15:0] stream. It is not necessary for TSOC to be present for each cell. An interrupt may be generated if TSOC is high during any word other than the first word of the cell structure. TSOC is sampled on the rising edge of TFCLK and is considered valid only when TWRENB is simultaneously asserted. TCA Output 67 The transmit cell available (TCA) signal indicates when a cell is available in the transmit FIFO. When high, TCA indicates that the transmit FIFO is not full. When TCA goes low, it indicates that either the transmit FIFO is near full and can accept no more than four writes or that the transmit FIFO is full. Selection is made using a register bit. In addition, to reduce FIFO latency, the FIFO full level can be programmed using bits in the FIFO register. TCA is updated on the rising edge of TFCLK. The active polarity of TCA is programmable and defaults to active-high. The TCA output is asserted (set high) when the S/UNI-622 is reset. XOFF RTOH[1] RTOH[2] RTOH[3] RTOH[4] Input Output 63 156 155 154 The XOFF pin should not be used, and must be forced low. The receive transport overhead bus (RTOH[4:1]) contains the receive transport overhead bytes (A1, A2, C1, B1, E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1, Z2, and E2) extracted from the incoming stream. When STS-12c (STM-4c) mode is selected, RTOH[1] contains the transport 153 overhead from STS-3 (STM-1) #1, RTOH[2] contains the transport overhead for STS-3 (STM-1) #2, RTOH[3] contains the transport overhead for STS-3 (STM-1) #3, and RTOH[4] contains the transport overhead for STS-3 (STM-1) #4. When STS-3c (STM-1) or STS-1 mode is selected, RTOH[1] contains all the transport overhead bytes. RTOH[4:2] are not used. RTOH[4:1] is updated on the falling edge of RTOHCLK. RTOHCLK Output 157 The receive transport overhead clock (RTOHCLK) is nominally a 5.184 MHz clock (STS-12c/STS-3c) or a 1.728 MHz clock (STS-1) which provides timing to process the extracted receive transport overhead. When STS-12c (STM-4c) or STS-3c (STM-1) mode is selected, RTOHCLK is a gapped 6.48 MHz clock. When STS-1 mode is selected, RTOHCLK is a gapped 2.16 MHz clock. RTOHCLK is updated on the falling edge of GROCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function RTOHFP Output 158 The receive transport overhead frame position (RTOHFP) signal is used to locate the individual receive transport overhead bits in the transport overhead bus, RTOH[4:1]. RTOHFP is set high while bit 1 (the most significant bit) of the first framing byte (A1) is present in the RTOH[4:1] stream. RTOHFP is updated on the falling edge of RTOHCLK. RPOH Output 181 The receive path overhead data (RPOH) signal contains the path overhead bytes (J1, B3, C2, G1, F2, H4, Z3, Z4 and Z5) extracted from the received STS-12c/3c/1 frame. RPOH is updated on the falling edge of RPOHCLK. RPOHCLK Output 176 The receive path overhead clock (RPOHCLK) is nominally a 576 kHz clock which provides timing to process the extracted receive path overhead. RPOHCLK is a gapped 648 KHz clock. RPOHCLK is updated on the falling edge of GROCLK. RPOHFP Output 177 The receive path overhead frame position (RPOHFP) signal may be used to locate the individual receive path overhead bits in the path overhead data stream, RPOH. RPOHFP is logic one while bit 1 (the most significant bit) of the path trace byte (J1) is present in the RPOH stream. RPOHFP is updated on the falling edge of RPOHCLK. RSDCLK Output 159 The receive section DCC clock (RSDCLK) is a 192 kHz clock used to update the RSD output. RSDCLK is generated by gapping a 216 kHz clock. RSD Output 160 The receive section DCC (RSD) signal contains the serial section data communications channel (D1, D2 D3) extracted from the incoming stream. RSD is updated on the falling edge of RSDCLK. RLDCLK Output 173 The receive line DCC clock (RLDCLK) is a 576 kHz clock used to update the RLD output. RLDCLK is generated by gapping a 2.16 MHz clock. RLD Output 172 The receive line DCC (RLD) signal contains the serial line data communications channel (D4 - D12) extracted from the incoming stream. RLD is updated on the falling edge of RLDCLK. ROWCLK Output 168 The receive order wire clock (ROWCLK) is a 64 kHz clock used to update the RSOW, RSUC, and RLOW outputs. ROWCLK is generated by gapping a 72 kHz clock. RSOW Output 162 The receive section order wire (RSOW) signal contains the section order wire channel (E1) extracted from the incoming stream. RSOW is updated on the falling edge of ROWCLK. RSUC Output 161 The receive section user channel (RSUC) signal contains the section user channel (F1) extracted from the incoming stream. RSUC is updated on the falling edge of ROWCLK. RLOW Output 167 The receive line order wire (RLOW) signal contains the line order wire channel (E2) extracted from the incoming stream. RLOW is updated on the falling edge of ROWCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function OHFP Output 175 The overhead frame pulse (OHFP) signal identifies the start of a byte on outputs RSOW, RSUC and RLOW. If required, OHFP is one GROCLK clock cycle wide and can be used as a reset pulse for an external counter. Please refer to the functional timing diagrams for details. TTOH[4] TTOH[3] TTOH[2] TTOH[1] Input 83 84 85 86 The transmit transport overhead bus (TTOH[4:1]) contains the transport overhead bytes (A1, A2, C1, E1, F1, D1-D3, H3, K1, K2, D4-D12, Z1, Z2 and E2) and error masks (H1, H2, B1 and B2) which may be inserted or used to insert bit interleaved parity errors or payload pointer bit errors into the overhead byte positions in the outgoing stream. Insertion is controlled by the TTOHEN input. When STS-12c (STM-4c) mode is selected, TTOH[1] contains the transport overhead for STS-3 (STM-1) #1. TTOH[2] contains the transport overhead for STS-3 (STM-1) #2. TTOH[3] contains the transport overhead for STS-3 (STM-1) #3. TTOH[4] contains the transport overhead for STS-3 (STM-1) #4. When STS-3c (STM-1) or STS-1 mode is selected, TTOH[1] contains all the transport overhead bytes. TTOH[4:2] are not used. The TTOH[4:1] inputs are sampled on the rising edge of TTOHCLK. TTOHEN Input 101 The transmit transport overhead insert enable (TTOHEN) signal, together with internal register bits, controls the source of the transport overhead data which is transmitted. While TTOHEN is high, values sampled on the TTOH[4:1] input bus are inserted into the corresponding transport overhead bit position (for the A1, A2, C1, E1, F1, D1-D3, K1, K2, H3, D4-D12, Z1, Z2 and E2 bytes). While TTOHEN is low, default values are inserted into these transport overhead bit positions. A high level on TTOHEN during the B1, B2 or H1-H2 bit positions enables an error mask. While an error mask is enabled, a high level on input TTOH causes the corresponding B1, B2 or H1-H2 bit position to be inverted. A low level on TTOH allows the corresponding bit position to pass through the S/UNI-622 uncorrupted. TTOHEN is sampled on the rising edge of TTOHCLK. TTOHCLK Output 99 The transmit transport overhead clock (TTOHCLK) is nominally a 5.184 MHz clock (STS-12c/STS-3c) or a 1.728 MHz clock (STS-1) clock which provides timing for upstream circuitry that sources the transport overhead stream, TTOH[4:1]. When STS-12c (STM-4c) or STS-3c (STM-1) mode is selected, TTOHCLK is a gapped 6.48 MHz clock. When STS-1 mode is selected, TTOHCLK is a gapped 2.16 MHz clock. TTOHCLK is updated in the rising edge of TCLK. TTOHFP Output 100 The transmit transport overhead frame position (TTOHFP) signal is used to locate the individual transport overhead bits in the transport overhead bus, TTOH[4:1]. TTOHFP is set high while bit 1 (the most significant bit) of the first framing byte (A1) is expected in the incoming stream. TTOHFP is updated on the falling edge of TTOHCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function TPOH Input 82 The transmit path overhead data (TPOH) signal contains the path overhead bytes (J1, C2, G1, F2, Z3, Z4 and Z5) and error masks (B3 and H4) which may be inserted or used to insert path BIP-8 or multiframe bit errors into the path overhead byte positions in the STS-12c/3c/1 stream. Insertion is controlled by the TPOHEN input, or by bits in internal registers. TPOH is sampled on the rising edge of TPOHCLK. TPOHEN Input 77 The transmit path overhead insert enable (TPOHEN) signal, together with internal register bits, controls the source of the path overhead data which is inserted in the POUT[7:0] stream. While TPOHEN is high, values sampled on the TPOH input are inserted into the corresponding path overhead bit position (for the J1, C2, G1, F2, Z3, Z4 and Z5 bytes). While TPOHEN is low, values obtained from internal registers are inserted into these path overhead bit positions. A high level on TPOHEN during the H4 or B3 bit positions enables an error mask. While an error mask is enabled, a high level on input TPOH causes the corresponding B3 or H4 bit position to be inverted. A low level on TPOH allows the corresponding bit position to pass through the S/UNI-622 uncorrupted. TPOHEN is sampled on the rising edge of TPOHCLK. TPOHCLK Output 75 The transmit path overhead clock (TPOHCLK) is nominally a 576 kHz clock which provides timing for upstream circuitry that sources the path overhead stream, TPOH. TPOHCLK is a gapped 810 kHz clock. TPOHCLK is updated in the falling edge of GROCLK. TPOHFP Output 76 The transmit path overhead frame position (TPOHFP) signal may be used to locate the individual path overhead bits in the path overhead data stream, TPOH. TPOHFP is logic one while bit 1 (the most significant bit) of the path trace byte (J1) is expected in the TPOH stream. TPOHFP is updated on the falling edge of TPOHCLK. TOWCLK Output 95 The transmit order wire clock (TOWCLK) is a 64 kHz clock used to sample the TSOW, TSUC, and TLOW inputs. TOWCLK is generated by gapping a 72 kHz clock. TSOW Input 94 The transmit section order wire (TSOW) signal contains the section order wire channel (E1) inserted into the outgoing stream. When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH[1] and TTOHEN takes precedence over overhead sourced using TSOW. TSOW is sampled on the rising edge of TOWCLK. TSUC Input 93 The transmit section user channel (TSUC) signal contains the section user channel (F1) inserted into the outgoing stream. When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH[1] and TTOHEN takes precedence over overhead sourced using TSUC. TSUC is sampled on the rising edge of TOWCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function TLOW Input 92 The transmit line order wire (TLOW) signal contains the line order wire channel (E2) inserted into the outgoing stream. When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH[1] and TTOHEN takes precedence over overhead sourced using TLOW. TLOW is updated on the rising edge of TOWCLK. TSDCLK Output 102 The transmit section DCC clock (TSDCLK) is a 192 kHz clock used to sample the TSD input. TSDCLK is generated by gapping a 216 kHz clock. TSD Input 103 The transmit section DCC (TSD) signal contains the serial section data communications channel (D1, D2 D3). When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH[1] and TTOHEN takes precedence over overhead sourced using TSD. TSD is sampled on the rising edge of TSDCLK. TLDCLK Output 90 The transmit line DCC clock (TLDCLK) is a 576 kHz clock used to sample the TLD input. TLDCLK is generated by gapping a 2.16 MHz clock. TLD Input 91 The transmit line DCC (TLD) signal contains the serial line data communications channel (D4 - D12). When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH[1] and TTOHEN takes precedence over overhead sourced using TLD. TLD is sampled on the rising edge of TLDCLK. RCP Output 187 The receive cell pulse (RCP) signal marks the most significant bit (MSB) of a cell header's GFC field on output, RGFC. RCP is updated on the falling edge of GROCLK. RGFC Output 193 The receive generic flow control (RGFC) signal contains the serialized GFC field extracted from receive cells. The GFC field is output MSB first. The RCP output identifies the MSB of every GFC field. The GFC Control register can be used to gate off individual GFC bits. When the S/UNI-622 is in the OCD state, RGFC is forced low. RGFC is updated on the falling edge of GROCLK. TCP Output 68 The transmit cell pulse (TCP) signal is provided to locate the most significant GFC bit (GFC[3]) of a cell's GFC field sourced on input TGFC. TCP pulses high for one GTOCLK period to identify the GTOCLK cycle before the cycle the GFC[3] bit is output on TGFC. TCP is updated on the falling edge of GTOCLK. TGFC Input 62 The transmit generic flow control (TGFC) input contains GFC bits that can be inserted into the GFC fields of transmitted cells (including idle/unassigned cells). Insertion is controlled using bits in the TACP Fixed Stuff/GFC register. TGFC is sampled on the rising edge of GTOCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function POP[5] POP[4] POP[3] POP[2] POP[1] POP[0] PIP[3] PIP[2] PIP[1] PIP[0] CSB Output 130 131 132 133 134 135 The parallel output port (POP[5:0]) is used to control the operation of front end line devices. The signal levels on this parallel output port correspond to the bit values contained in the S/UNI-622 Parallel Output Port Register. Input 105 106 107 108 The parallel input port (PIP[3:0]) is used to monitor the operation of front end line devices. An interrupt may be generated when state changes are detected on the monitored signals. State changes and the real-time signal levels on this port are available via the S/UNI-622 Parallel Input Port register. Input 36 The active-low chip select (CSB) signal is low during S/UNI-622 register accesses. Note that when not being used, CSB must be tied high. If CSB is not required (i.e., registers accesses are controlled using the RDB and WRB signals only), CSB must be connected to an inverted version of the RSTB input. RDB Input 38 The active-low read enable (RDB) signal is low during S/UNI-622 register read accesses. The S/UNI-622 drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. WRB Input 37 The active-low write strobe (WRB) signal is low during a S/UNI-622 register write accesses. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] I/O 23 24 25 26 31 32 33 34 The bidirectional data bus D[7:0] is used during S/UNI-622 register read and write accesses. Input 15 16 17 18 19 20 21 The address bus A[7:0] selects specific registers during S/UNI-622 register accesses. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function A[7]/TRS 22 The test register select (TRS) signal selects between normal and test mode register accesses. TRS is high during test mode register accesses, and is low during normal mode register accesses. RSTB Input 35 The active-low reset (RSTB) signal provides an asynchronous S/UNI-622 reset. RSTB is a Schmitt triggered input with an integral pull-up resistor. ALE Input 14 The address latch enable (ALE) is active-high and latches the address bus A[7:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-622 to interface to a multiplexed address/data bus. ALE has an integral pull-up resistor. INTB OD Output 39 The active-low interrupt (INTB) signal goes low when a S/UNI-622 interrupt source is active and that source is unmasked. The S/UNI-622 may be enabled to report many alarms or events via interrupts. Examples are loss of signal (LOS), loss of frame (LOF), line AIS, line remote defect indication (LRDI) detect, loss of pointer (LOP), path AIS, path remote defect indication detect and others. INTB is tristated when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. TCK Input 70 The test clock (TCK) signal provides timing for test operations that are carried out using the IEEE P1149.1 test access port. TMS Input 126 The test mode select (TMS) signal controls the test operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor. TDI Input 127 The test data input (TDI) signal carries test data into the S/UNI-622 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor. TDO Tristate 71 The test data output (TDO) signal carries test data out of the S/UNI-622 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress. TRSTB Input 125 The active-low test reset (TRSTB) signal provides an asynchronous S/UNI-622 test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor. Note that when not being used, TRSTB must be connected to the RSTB input. BUS8 Input 69 This pin must be connected to GND for proper operation of the S/UNI-622 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function VDD_AC1 VDD_AC2 VDD_AC3 VDD_AC4 VDD_AC5 VDD_AC6 VDD_AC7 VSS_AC1 VSS_AC2 VSS_AC3 VSS_AC4 VSS_AC5 VSS_AC6 VSS_AC7 VDD_DC1 VDD_DC2 VDD_DC3 VDD_DC4 VDD_DC5 VDD_DC6 VDD_DC7 VDD_DC8 VDD_DC9 VDD_DC10 VDD_DC11 VDD_DC12 VDD_DC13 VDD_DC14 Power 10 27 81 120 152 183 205 The AC power (VDD_AC1 - VDD_AC7) pins should be connected to a welldecoupled +5 V DC supply in common with VDD_DC. Ground 13 30 78 117 151 184 208 The AC ground (VSS_AC1 - VSS_AC7) pins should be connected to GND in common with VSS_DC. Power 11 28 40 66 80 98 110 119 129 138 165 179 189 206 The DC power (VDD_DC1 - VDD_DC14) pins should be connected to a welldecoupled +5 V DC supply in common with VDD_AC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Pin Name Type Pin No. Function VSS_DC1 VSS_DC2 VSS_DC3 VSS_DC4 VSS_DC5 VSS_DC6 VSS_DC7 VSS_DC8 VSS_DC9 VSS_DC10 VSS_DC11 VSS_DC12 VSS_DC13 VSS_DC14 Ground 12 29 41 64 79 96 109 118 128 136 166 180 191 207 The DC ground (VSS_DC1 - VSS_DC14) pins should be connected to GND in common with VSS_AC. Notes on Pin Description: 1. All S/UNI-622 inputs and bidirectionals present minimum capacitive loading and operate at TTL logic levels. 2. All S/UNI-622 outputs and bidirectionals have at least 2 mA drive capability. The data bus outputs, D[7:0], have 4 mA drive capability. The FIFO interface outputs, RDAT[15:0], RXPRTY[1:0], RCA, RSOC, and TCA, have 4 mA drive capability. Outputs POUT[7:0], FPOUT, TSOUT, GTOCLK and GROCLK also have 4 mA drive capability 3. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors. 4. The VSS_DC and VSS_AC ground pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the S/UNI-622. 5. The VDD_DC and VDD_AC power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the S/UNI-622. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9 9.1 FUNCTIONAL DESCRIPTION Receive Section Overhead Processor The Receive Section Overhead Processor (RSOP) provides frame synchronization, descrambling, section level alarm and performance monitoring. In addition, it extracts the section orderwire channel, the section user channel, the section data communication channel from the section overhead and provides them serially on outputs RSOW, RSUC and RSD, respectively. The RSOP is intended to operate with an upstream device which performs clock and data recovery, deserialization and preframing (to the A1 and A2 framing bytes). 9.1.1 Framer The Framer Block determines the in-frame/out-of-frame status of the STS-12c/3c/1 data stream. Output OOF reflects this status, and is updated with timing aligned to PICLK. While out of frame, upstream circuitry monitors the bit-serial STS-12c/3c/1 data stream for an occurrence of the framing pattern (A1, A2). The upstream circuitry is expected to pulse input FPIN when a framing pattern has been detected to reinitializes the channel counter to the new alignment. The Framer block declares frame alignment when either all A1 and A2 bytes are seen error-free or when only the first A1 byte and the first four bits of the first A2 byte are seen error-free depending upon the selected framing algorithm. The first algorithm examines 24, 6 or 2 bytes depending on the mode, while the second algorithm examines only the first occurrence of A1 and the first four bits of the first occurrence of A2 in the sequence regardless of the mode. Once in frame, the Framer block monitors the framing pattern sequence and declares OOF when one or more bit errors in each framing pattern are detected for four consecutive frames. Again, depending upon the algorithm either 24 framing bytes are examined for bit errors each frame, or only the first A1 byte and the first four bits of the first A2 byte are examined for bit errors each frame. The performance of these framing algorithms in the presence of bit errors and random data is robust. When looking for frame alignment, the performance of each algorithm is dominated by the alignment algorithm used by the upstream circuitry. Once in frame alignment, the Framer block continuously monitors the framing pattern. When the incoming stream contains a 10-3 bit error rate (BER), the first algorithm provides a mean time between OOF occurrences of 4 minutes for STS-1 mode, 14 seconds for STS-3c (STM-1) mode and 0.13 seconds for PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) STS-12c (STM-4c) mode. The second algorithm provides a mean time between OOF occurrences of 103 minutes independent of operating mode. 9.1.2 Descramble The Descramble Block utilizes a frame synchronous descrambler to process the received byte-serial stream. The generating polynomial is 1 + x6 + x7 and the sequence length is 127. Details of the descrambling operation are provided in the references. Note that the framing bytes (A1 and A2) and the identity bytes (C1) are not descrambled. A register bit is provided to disable the descrambling operation. 9.1.3 Error Monitor The Error Monitor Block calculates the received section BIP-8 error detection code (B1) based on the scrambled data of the complete STS-12c/3c/1 frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 code is compared with the BIP-8 code extracted from the B1 byte of the following frame. Differences indicate that a section level bit error has occurred. Up to 64000 (8 x 8000) bit errors can be detected per second. The Error Monitor Block accumulates these section level bit errors in a 16-bit saturating counter that can be read via the microprocessor interface. Circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to 0 or 1, if appropriate, so that a new period of accumulation can begin without losing any events. It is intended that this counter be polled at least once per second so that bit error events are not missed. 9.1.4 Loss of Signal The Loss of Signal Block monitors the scrambled data of the complete STS-12c/3c/1 stream for the absence of ones. When 20 3 s of all zeros patterns is detected, a loss of signal (LOS) is declared. Loss of signal is cleared when two valid framing words are detected and during the intervening time, no loss of signal condition is detected. LOS is updated with timing aligned to PICLK. 9.1.5 Loss of Frame The Loss of Frame Block monitors the in-frame/out-of-frame status of the Framer Block. A loss of frame (LOF) is declared when an out-of-frame (OOF) condition persists for 3 ms. To provide for intermittent out-of-frame conditions, the 3 ms PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) timer is not reset to zero until an in-frame condition persists for 3 ms. The loss of frame is cleared when an in-frame condition persists for a period of 3 ms. LOF indication is updated with timing aligned to PICLK. 9.2 Receive Line Overhead Processor The Receive Line Overhead Processor (RLOP) provides line level alarm and performance monitoring. In addition, it extracts the line orderwire channel and the line data communication channel from the line overhead and provides them serially on outputs RLOW and RLD respectively. 9.2.1 Line RDI Detect The LRDI Detect Block detects the presence of line remote defect indications in the STS-12c/3c/1 stream. Output LRDI is asserted when a 110 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for five consecutive frames. Line RDI is removed when any pattern other than 110 is detected in bits 6, 7 and 8 of the K2 byte for five consecutive frames. LRDI is updated with timing aligned to PICLK. 9.2.2 Line AIS Detect The Line AIS Block detects the presence of a Line Alarm Indication Signal (AIS) in the STS-12c/3c/1 stream. Output LAIS is asserted when a 111 binary pattern is detected in bits 6, 7 8 of the K2 byte for five consecutive frames. LAIS is removed when any pattern other than 111 is detected in bits 6, 7 and 8 of the K2 byte for five consecutive frames. LAIS is updated with timing aligned to PICLK. 9.2.3 Automatic Protection Switch Control Block The Automatic Protection Switch Control (APSC) Block filters and captures the receive automatic protection switch channel bytes (K1 and K2) and allows them to be read via the S/UNI-622 Receive K1 Register and the S/UNI-622 Receive K2 Register. The bytes are filtered for three frames before being written to these registers. A protection switching byte failure alarm is declared when twelve successive frames have been received in which no three consecutive frames contain identical K1 bytes. The protection switching byte failure alarm is removed upon detection of three consecutive frames containing identical K1 bytes. The detection of invalid APS codes is done in software by polling the S/UNI-622 Receive K1 Register and the S/UNI-622 Receive K2 Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.2.4 Error Monitor The Error Monitor Block calculates the received line BIP error detection code (B2) based on the line overhead and synchronous payload envelope of the STS-12c/3c/1 stream. The line BIP code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP code is compared with the BIP code extracted from the STS-12c/3c/1 of the following frame. Any differences indicate that a line layer bit error has occurred. Up to 768000 (12 x 8 x 8000) bit errors can be detected per second. The Error Monitor Block accumulates these line layer bit errors in a 16-bit saturating counter that can be read via the microprocessor interface. During a read, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note that this counter should be polled at least once per second to avoid saturation which in turn may result in missed bit error events. The Error Monitor Block also accumulates line far end block error indications (contained in the Z2 byte). 9.3 Byte Interleaved Demultiplexer The Byte Interleaved Demultiplexer block (BIDX) is only active when STS-12c (STM-4c) mode is selected. It performs a 1:4 byte-serial to word- (four byte) serial demultiplexing function on the incoming byte-serial STS-12c data stream. The demultiplexed streams with a divide-by-four clock are made available to downstream blocks for lower rate processing. 9.4 Transport Overhead Extract Port The Transport Overhead Extract Port ( also known as the Receive Transport Overhead Access Port, RTOP) extracts the entire receive transport overhead on the RTOH[4:1] bus for optional external processing. Output RTOHFP is provided to identify the most significant bit of the A1 framing bytes on RTOH[4:1]. The transport overhead clock, RTOHCLK is nominally a 5.184 MHz (STS-12c, STS-3c modes) or a 1.728 MHz (STS-1 mode) clock. RTOH[4:1] and RTOHFP are updated with timing aligned to RTOHCLK. 9.5 Receive Path Overhead Processor The Receive Path Overhead Processor (RPOP) provides pointer interpretation, extraction of path overhead, and path level alarm indication. In conjunction with the Receive Concatenation Processor (RCOP) sub block, the RPOP also PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) identifies the synchronous payload envelope and monitors the performance of the STS-12c/3c/1 line. 9.5.1 Pointer Interpreter The Pointer Interpreter Block interprets the incoming pointer (H1, H2) as specified in the references. The pointer value is used to determine the location of the path overhead (the J1 byte) in the incoming STS-12c/3c/1 stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm three states are defined as shown in Figure 6: NORM_state (NORM) AIS_state (AIS) LOP_state (LOP) The transition between states will be consecutive events (indications), e.g., three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is chosen such that the behaviour is stable and insensitive to low BER. The only transition on a single event is the one from the AIS_state to the NORM_state after receiving a NDF enabled with a valid pointer value. It should be noted that, since the algorithm only contains transitions based on consecutive indications, nonconsecutively received invalid indications do not activate the transitions to the LOP_state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 33 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 6 - Pointer Interpretation State Diagram 3 x eq_new _po int inc_in d / dec _ind N D F _enab le NORM eq 3x _n ND 8x in v _ po int b le ew F_ e na nt _ A IS 3x _p en po i o in 8x ND F_ ab 3x e q_ new _ t le in d 3 x A IS _ind LO P A IS 8 x inv_point The following events (indications) are defined norm_point: NDF_enable: AIS_ind: inc_ind: disabled NDF + ss + offset value equal to active offset enabled NDF + ss + offset value in range of 0 to 782 H1 = 'hFF, H2 = 'hFF disabled NDF + ss + majority of I bits inverted + no majority of D bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) dec_ind: disabled NDF + ss + majority of D bits inverted + no majority of I bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago not any of above (i.e., not norm_point, and not NDF_enable, and not AIS_ind, and not inc_ind and not dec_ind) disabled_NDF + ss + offset value in range of 0 to 782 but not equal to active offset. active offset is defined as the accepted current phase of the SPE in the NORM_state and is undefined in the other states. enabled NDF is defined as the following bit patterns: 1001, 0001, 1101, 1011, 1000. disabled NDF is defined as the following bit patterns: 0110, 1110, 0010, 0100, 0111. the remaining six NDF codes (0000, 0011, 0101, 1010, 1100, 1111) result in an inv_point indication. ss bits are unspecified in SONET and has bit pattern 10 in SDH the use of ss bits in definition of indications may be optionally disabled. the requirement for previous NDF_enable, inc_ind or dec_ind be more than 3 frames ago may be optionally disabled. new_point is also an inv_point. inv_point: new_point: Note 1.- Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 - Note 8 - The transitions indicated in the state diagram are defined as follows: inc_ind/dec_ind: offset adjustment (increment or decrement indication) 3 x eq_new_point: three consecutive equal new_point indications NDF_enable: 3 x AIS_ind: single NDF_enable indication three consecutive AIS indications PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 8 x inv_point: 8 x NDF_enable Note 1 Note 2 Note 3 Note 4 - eight consecutive inv_point indications eight consecutive NDF_enable indications the transitions from NORM_state to NORM_state do not represent state changes but imply offset changes. 3 x new_point takes precedence over 8 x inv_point. all three offset values received in 3 x eq_new_point must be identical. "consecutive event counters" are reset to zero on a change of state. The Pointer Interpreter Block detects loss of pointer (LOP) in the incoming STS-12c/3c/1 stream. LOP is declared (LOP output set high) on entry to the LOP_state as a result of eight consecutive invalid pointers or eight consecutive NDF enabled indications. LOP is removed (LOP output set low) when the same valid pointer with normal NDF is detected for three consecutive frames. Incoming STS Path AIS (pointer bytes set to all ones) does not cause entry into the LOP state. The Pointer Interpreter Block detects path AIS in the incoming STS-12c/3c/1 stream. PAIS is declared (PAIS output set high) on entry to the AIS_state after three consecutive AIS indications. PAIS is removed (PAIS set low) when the same valid pointer with normal NDF is detected for three consecutive frames or when a valid pointer with NDF enabled is detected. Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications (new_point), discontinuous change of pointer alignment, and illegal pointer changes are also detected and reported by the Pointer Interpreter block via register bits. An invalid NDF code is any NDF code that does not match the NDF enabled or NDF disabled definitions. The third occurrence of equal new_point indications (3 x eq_new_point) is reported as a discontinuous change of pointer alignment event (DISCOPA) instead of a new pointer event and the active offset is updated with the receive pointer value. An illegal pointer change is defined as a inc_ind or dec_ind indication that occurs within three frames of the previous inc_ind, dec_ind or NDF_enable indications. Illegal pointer changes may be optionally disabled via register bits. The pointer value is used to extract the path overhead from the incoming stream. The current pointer value can be read from an internal register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) The ATM Forum 622.08 Mbps Physical Layer Specification states that the receiving equipment supporting the private/public UNI or the private NNI shall check for the concatenation indication when interpreting the pointer as specified in ANSI T1.105 and ITU G.709. T1.105 requires that one monitor the concatenation indication bytes H1* and H2* but does not specify any action when an error occurs. Hence the S/UNI-622 is compatible with the ANSI T1.105 concatenation indication specification. ITU G.709 refers one to ITU G.783. The G.783 document defines, in Annex B, a state diagram, illustrated below, for the interpretation of the concatenation pointers H1* and H2*. This functionality is not contained in the S/UNI-622 but can be realized externally as illustrated in Figure 8. Figure 7 - ITU G.783 Concatenation Indicator State Diagram CONC co 3x nc in t at_ _ po d _ in A IS 3x in d Nx in v 3x c on c _i nc 3 x A IS _ind LO PC A IS C N x inv_po int PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 8 - ITU G.783 Concatenation Indicator Implementation Ext ernal L ogic " RX T OH" L OPC AISC PM5 3 5 5 S / UNI- 6 2 2 " LOP" L OP " AIS " AIS 9.5.2 SPE Timing The SPE Timing Block provides SPE timing information to the Error Monitor and the Extract blocks. The block contains a free-running timeslot counter that is initialized by a J1 byte identifier (which identifies the first byte of the SPE). Control signals are provided to the Error Monitor and the Extract blocks to identify the Path Overhead bytes and to downstream circuitry to extract the ATM cell payload. 9.5.3 Error Monitor The Error Monitor Block contains two 16-bit counters that are used to accumulate path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two counters may be transferred to holding registers, and the counters reset under microprocessor control. Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted from the current frame, to the path BIP-8 computed for the previous frame. The RPOP block performs the BIP-8 calculation over the STS-3c #1 portion of the SPE while the RCOP sub block performs the calculation over the remaining STS-3c #2, #3 and #4 portions of the SPE. The two calculations are combined by the RPOP to form the final BIP-8 code. FEBEs are detected by extracting the 4-bit FEBE field from the path status byte (G1). The legal range for the 4-bit field is between 0 (0000B) and 8 (1000B), representing zero to eight errors. Any other value is interpreted as zero errors. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) The path remote defect indication is detected by extracting bit 5 of the path status byte. The PRDI signal is set high when bit 5 is set high for five (or ten) consecutive frames. PRDI is set low when bit 5 is low for five (or ten) consecutive frames. PRDI is updated with timing aligned to GROCLK. 9.6 Path Overhead Extract The Path Overhead Extract Block uses timing information from the SPE Timing block to extract, serialize and output the Path Overhead bytes on output RPOH. Output RPOHFP is provided to identify the most significant bit of the path trace byte (J1) on RPOH. The path overhead clock, RPOHCLK is nominally a 576 kHz clock. RPOH and RPOHFP are updated with timing aligned to RPOHCLK. 9.7 Receive ATM Cell Processor The Receive ATM Cell Processor (RACP) performs ATM cell delineation, provides cell filtering based on idle/unassigned cell detection and HCS error detection, and performs ATM cell payload descrambling. The RACP also provides a four-cell deep receive FIFO. This FIFO is used to separate the STS-12c/3c/1 line timing from the higher layer ATM system timing. The cells are passed in a twenty-seven word cell structure where a word is sixteen bits. 9.7.1 Cell Delineation Cell delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the cell header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. Cells must be byte aligned before insertion in the synchronous payload envelope. The cell delineation algorithm searches the 53 possible cell boundary candidates one by one to determine the valid cell boundary location. While searching for the cell boundary location, the cell delineation circuit is in the HUNT state. When a correct HCS is found, the cell delineation state machine locks onto the particular cell boundary and enters the PRESYNC state. This state validates the cell boundary location. If the cell boundary is invalid, an incorrect HCS will be received within the next DELTA cells, at which point a transition back to the HUNT state is executed. If no HCS errors are detected in this PRESYNC period, the SYNC state is entered. While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in Figure 9. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 9 - Cell Delineation State Diagram correct HCS (byte by byte) HUNT Incorrect HCS (cell by cell) PRESYNC ALPHA consecutive incorrect HCS's (cell by cell) SYNC DELTA consecutive correct HCS's (cell by cell) The values of ALPHA and DELTA determine the robustness of the delineation method. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is 7, and DELTA is 6. These values result in a maximum average time to delineate of 8 s. 9.7.2 Descrambler The self synchronous descrambler operates on the 48-byte cell payload only. The circuitry descrambles the information field using the polynomial x43 + 1. The descrambler is disabled for the duration of the header and HCS fields, and may optionally be disabled. 9.7.3 Cell Filter and HCS Verification Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern. Cell filtering is optional and is enabled through the RACP registers. Cells are passed to the receive FIFO while the cell delineation state machine is in the SYNC state as described above. When both filtering and HCS checking are enabled, cells are dropped if uncorrectable HCS errors are detected, or if the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) corrected header contents match the pattern contained in the RACP Match Header Pattern and RACP Match Header Mask registers. Idle or unassigned cell filtering is accomplished by writing the appropriate cell header pattern into the RACP Match Header Pattern and RACP Match Header Mask registers. Idle/Unassigned cells are assumed to contain the all-zeros pattern in the VCI and VPI fields. The RACP Match Header Pattern and RACP Match Header Mask registers allow filtering control over the contents of the GFC, PTI and CLP fields of the header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RACP block verifies the received HCS using the polynomial, x 8 + x2 + x + 1. The coset polynomial, x6 + x4 + x2 + 1 is added (modulo 2) to the received HCS octet before comparison with the calculated result. While the cell delineation state machine (described above) is in the SYNC state, the HCS verification circuit implements the state machine shown in Figure 10: Figure 10 - HCS Verification State Diagram ATM DELINEATION SYNC STATE ALPHA consecutive incorrect HCS's (To HUNT state) Apparent Multi-Bit Error (Drop Cell) No Errors Detected (Pass Cell) CORRECTION MODE Single-Bit Error (Correct Error and Pass Cell) Errors Detected (Drop Cell) DETECTION MODE DELTA consecutive correct HCS's (From PRESYNC state) No Errors Detected In M Cells th (Pass M Cell) No Errors Detected (Pass Cell) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) In normal operation, the HCS verification state machine remains in the 'Correction Mode' state. Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single- bit error or a multi-bit error, the state machine transitions to the 'Detection Mode' state. In this state, programmable HCS error filtering is provided. The detection of any HCS error causes the corresponding cell to be dropped. The state machine transitions back to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received with correct HCSs. The Mth cell is not discarded. 9.7.4 Performance Monitor The Performance Monitor consists of two 12-bit saturating HCS error event counters. One of the counters accumulates correctable HCS errors which are single-bit HCS errors detected while the HCS Verification state machine is in the 'Correction Mode' state described above. The second counter accumulates uncorrectable HCS errors which are HCS bit errors detected while the HCS Verification state machine is in the 'Detection Mode' state or multiple bit HCS errors detected while the state machine is in the 'Correction Mode' state as described above. Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without the loss of any events. It is intended that the counter be polled at least once per second so as not to miss HCS error events. 9.7.5 GFC Extraction Port The GFC Extraction Port outputs the received GFC bits in a serial stream. The four GFC bits are presented for each received cell, with the RCP output indicating the position of the most significant bit. Individual GFC bits may be masked through an internal register from appearing on the RGFC output. The serial output is forced low when an uncorrected cell is received or if cell delineation is lost. 9.7.6 Receive FIFO The Receive FIFO provides FIFO management and the asynchronous interface between the S/UNI-622 device and the external environment. The receive FIFO can accommodate four cells. The receive FIFO provides for the separation of the STS-12c/3c/1 line or physical layer timing from the ATM layer timing. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) The FIFO supports a data structure consists of twenty-seven 16-bit words consisting of the 5-octet cell header and the 48-octet payload (the HCS byte, along with the header status octet, is passed in this structure). Note that depending on the selected cell filtering options, the header status may be an 1) error-free header, 2) errored and corrected header, or 3) errored and uncorrectable header. Management functions include filling the receive FIFO, indicating when cells are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions. Upon detection of an overrun, the FIFO is automatically reset. Up to four cells may be lost during the FIFO reset operation. Upon detection of an underrun, the offending read is ignored. FIFO overruns are indicated through a maskable interrupt and register bits. The FIFO interface provided to the system is a synchronous interface emulating commercial synchronous FIFOs. All receive FIFO signals, RSOC, RRDENB, RCA, RXPRTY[1:0] and RDAT[15:0] are either sampled or updated on the rising edge of the RFCLK clock input. 9.8 Transmit Section Overhead Processor The Transmit Section Overhead Processor (TSOP) provides frame pattern insertion (A1, A2), scrambling, section level alarm signal insertion, and section BIP-8 (B1) insertion. It presents a STS-12c/3c/1 data stream in byte-serial format at 77.76-Mbyte/s to an off-chip serializer for transmission at the bit-serial rate. 9.8.1 Line AIS Insert Line AIS insertion results in all bits of the SONET/SDH frame, except for the section overhead, being set to one before scrambling. The Line AIS Insert Block substitutes all ones when enabled by the TLAIS input or through an internal register accessed through the microprocessor interface. Activation and deactivation of line AIS insertion is synchronized to frame boundaries. 9.8.2 BIP-8 Insert The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1) into the unscrambled STS-12c/3c/1 stream. The BIP-8 calculation is based on the scrambled data of the complete STS-12c/3c/1 frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. The calculated BIP-8 code is then inserted into the B1 byte of the following frame before scrambling. Details are provided in the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) references. BIP-8 errors may be continuously inserted under register control for diagnostic purposes. 9.8.3 Framing and Identity Insert The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and identity bytes (C1) into the STS-12c/3c/1 frame. Framing bit errors may be continuously inserted under register control for diagnostic purposes. 9.8.4 Scrambler The Scrambler Block utilizes a frame synchronous scrambler to process the transmit serial stream when enabled through an internal register accessed via the microprocessor interface. The generating polynomial is 1 + x6 + x7. Precise details of the scrambling operation are provided in the references. Note that the framing bytes and the identity bytes are not scrambled. The POUT[7:0] outputs are provided by the Scrambler Block and are updated with timing aligned to TCLK. It also provides the FPOUT signal. All zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes. 9.9 Transmit Line Overhead Processor The Transmit Line Overhead Processor (TLOP) provides line level alarm signal insertion and line BIP-96/24/8 insertion (B2). 9.9.1 APS Insert The APS Insert Block inserts the two automatic protection switch (APS) channel bytes in the Line Overhead (K1 and K2) into STS-1 #1 of the STS-12c/3c/1 stream when enabled by an internal register. 9.9.2 Line BIP Calculate The Line BIP Calculate Block calculates the line BIP-96/24/8 error detection code (B2) based on the line overhead and synchronous payload envelope of the STS-12c/3c/1 stream. The line BIP-96/24/8 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-96/24/8 code is inserted into the B2 byte positions of the following frame. BIP-96/24/8 errors may be continuously inserted under register control for diagnostic purposes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.9.3 Line RDI Insert The Line RDI Insert Block multiplexes the line overhead bytes into the STS-12c/3c/1 output stream and optionally inserts line RDI. Line RDI is inserted by this block when enabled via the TLRDI input or through register control. Line RDI is inserted by transmitting the code 110 (binary) in bit positions 6, 7 and 8 of the K2 byte contained in the STS-12c/3c/1 stream. 9.9.4 Line FEBE Insert The Line FEBE Insert Block accumulates line BIP-96/24/8 errors (Z2) detected by the Receive Line Overhead Processor and encodes far end block error indications in the transmit Z2 byte. 9.10 Byte Interleaved Multiplexer The Byte Interleaved Multiplexer block (BIMX) is only active when STS-12c (STM-4c) mode is selected. It performs a 4:1 (32-bit word to byte) multiplexing function on the incoming word serial stream from the Transmit Path Overhead Processor (TPOP) block. The resulting multiplexed byte-serial stream is passed to the Transmit Line Overhead Processor from which the line overhead (multiplexer section) is added to the stream. A generated transmit clock (GTOCLK) is provided for general use. GTOCLK is the supplied transmit clock, TCLK, divided down by four. 9.11 Transport Overhead Insert Port The Transport Overhead Insert Port (also known as the Transmit Transport Overhead Access Port, TTOP) allows the complete transport overhead to be inserted using the TTOH[4:1] bus, along with the transport overhead clock, TTOHCLK, and the transport overhead frame position, TTOHFP The transport . overhead clock, TTOHCLK, is nominally a 5.184 MHz (STS-12c and STS-3c modes) or a 1.728 MHz (STS-1 mode) clock. The transport overhead enable signal, TTOHEN, controls the insertion of transport overhead from the TTOH[4:1] bus. When configured for STS-3c (STM-1) or STS-1 mode, only TTOH[1] is required. The state of the TTOHEN input determines whether the data sampled on TTOH[4:1], or the default overhead byte values (shown in Figure 8) are inserted in the STS-12c/3c/1 stream. For example, when configured for STS-12c (STM-4c) mode, a high level on TTOHEN during the section user channel (F1) bit positions causes the eight values shifted in on each of the TTOH inputs to be PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) inserted into the four F1 byte position in the STS-12c stream. A low level on TTOHEN during the section user channel bit positions causes the default value (00H) to be inserted in the STS-12c stream. Other combinations are also possible. During the H1, H2, B1 and B2 byte positions in the TTOH[4:1] streams, a high level on TTOHEN enables an error insertion mask. While an error mask is enabled, a high level on inputs TTOH[4:1] causes the corresponding bits in the H1, H2, B1 or B2 byte to be inverted. A low level on inputs TTOH[4:1] causes the corresponding bits in the B1 or B2 byte to pass through the S/UNI-622 unmodified. Figure 11 - STS-12c (STM-4c) Default Transport Overhead Values A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 (F6) (F6) (F6) (F6) (F6) (F6) (F6) (F6) (F6) (F6) (F6) (F6) (28) (28) (28) (28) (28) (28) (28) (28) (28) (28) (28) (28) (*) (02) (03) (04) (05) (06) (07) (08) (09) (0A) (0B) (0C) B1 E1 F1 (*) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) D1 D2 D3 (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 (62) (93) (93) (93) (93) (93) (93) (93) (93) (93) (93) (93) (08) (FF) (FF) (FF) (FF) (FF) (FF) (FF) (FF) (FF) (FF) (FF) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 K1 K2 (**) (**) (**) (**) (**) (**) (**) (**) (**) (**) (**) (**) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) D4 D5 D6 (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) D8 D9 D7 (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) D10 D11 D12 (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z1 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 Z2 E2 (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (***) (00) (***) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) (00) C1 value defaults to 01 but can be programmed to to be the 16 or 64 byte section trace message. ** : B1, B2 values depend on payload contents ***: Z2 value depends on incoming line bit errors. When not configured for STS-1, the first Z2 byte has a default value of 00. *: 9.12 Transmit Path Overhead Processor The Transmit Path Overhead Processor (TPOP) provides transport frame alignment generation, pointer generation (H1, H2), path overhead insertion and the insertion of path level alarm signals. In conjunction with the Transmit Concatenation Processor (TCOP), the TPOP also provides for insertion of the synchronous payload envelope and path BIP-8 (B3) insertion. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.12.1 Pointer Generator The Pointer Generator Block generates the outgoing payload pointer (H1, H2). The block contains a free-running timeslot counter that locates the start of the synchronous payload envelope based on the generated pointer value and the SONET/SDH frame alignment. The Pointer Generator Block generates the outgoing pointer as specified in the references. The concatenation indication (the NDF field set to 1001, I-bits and D-bits set to all ones, and unused bits set to all zeros) is inserted in the second through twelfth pointer bytes. Rules 1 - 4 apply to the first pointer bytes of the STS-12c/3c/1 stream: 1. A "normal pointer value" locates the start of the SPE. Note: 0 "normal pointer value" 782, and the new data flag (NDF) field is set to 0110. Note that values greater than 782 may be inserted, using internal registers, to generate a loss of pointer alarm in downstream circuitry. 2. Arbitrary "pointer values" may be generated using internal registers. These new values may optionally be accompanied by a programmable new data flag. New data flags may also be generated independently using internal registers. 3. Positive pointer movements may be generated using a bit in an internal register. A positive pointer movement is generated by inverting the five I-bits of the pointer word. The SPE is not inserted during the positive stuff opportunity byte position, and the pointer value is incremented by one. Positive pointer movements may be inserted once per frame for diagnostic purposes. 4. Negative pointer movements may be generated using a bit in an internal register. A negative pointer movement is generated by inverting the five Dbits of the pointer word. The SPE is inserted during the negative stuff opportunity byte position, the H3 byte, and the pointer value is decremented by one. Negative pointer movements may be inserted once per frame for diagnostic purposes. The pointer value is used to insert the path overhead into the incoming stream. The current pointer value may be read via internal registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 47 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.12.2 BIP-8 Calculate The BIP-8 Calculate Block performs a path bit interleaved parity calculation on the STS-3c #1 portion of the outgoing STS-12c/3c/1 SPE stream. The TCOP sub block performs the calculation over the remaining STS-3c #2, #3 and #4 portions of the SPE. The resulting parity bytes are combined and inserted into the path BIP-8 (B3) byte position of the subsequent frame. BIP-8 errors may be continuously inserted under register control for diagnostic purposes. 9.12.3 FEBE Calculate The FEBE Calculate Block accumulates far end block errors on a per frame basis and inserts the accumulated value (up to maximum value of eight) in the FEBE bit positions of the path status (G1) byte. The FEBE information is derived from path BIP-8 errors detected by the receive path overhead processor, RPOP The . asynchronous nature of these signals implies that more than eight FEBE events may be accumulated between transmit G1 bytes. If more than eight receive Path BIP-8 errors are accumulated between transmit G1 bytes, the accumulation counter is decremented by eight, and the remaining FEBEs are transmitted at the next opportunity. Far end block errors may be inserted under register control for diagnostic purposes. 9.12.4 SPE Multiplexer The SPE Multiplexer Block multiplexes the payload pointer bytes, the SPE stream, and the path overhead bytes into the STS-12c/3c/1 stream. 9.13 Path Overhead Insert The Path Overhead Insert Block provides a bit-serial path overhead interface to the TPOP Any, or all, of the path overhead bytes may be sourced from, or . modified by, the bit-serial path overhead stream, TPOH. The individual bits of each path overhead byte are shifted in using the TPOHCLK output. The TPOHFP output is provided to identify when the most significant bit of the Path Trace byte is expected on TPOH. The state of the TPOHEN input, together with an internal register, determines whether the data sampled on TPOH, or the default path overhead byte values (shown in the table below) are inserted in the STS-12c/3c/1 stream. For example, a high level on TPOHEN during the path signal label (C2) bit positions causes the eight values shifted in on TPOH to be inserted in the C2 byte position in the STS-12c/3c/1 stream. A low level on TPOHEN during the path trace bit positions causes the default value (00H) to be inserted in the STS-12c/3c/1 stream. Other combinations are also possible. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 48 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Note, for the J1 byte, insertion can also be sourced from the SPTB block. J1 byte insertion via the TPOHEN input takes precedence over insertion via the SPTB block, which in turn takes precedence over insertion via the internal register source. During the B3 and H4 byte positions in the TPOH stream, a high level on TPOHEN enables an error insertion mask. While the error mask is enabled, a high level on input TPOH causes the corresponding bit in the B3 or H4 byte to be inverted. A low level on TPOH causes the corresponding bit in the B3 or H4 byte to pass through the TPOP unmodified. Figure 12 - Default Path Overhead Values J1 (*) B3 (**) C2 (13) G1 (***) F2 (00) H4 (00) Z3 (00) Z4 (00) Z5 (00) * J1 value defaults to 00H but can be programmed to be the 16 or 64 byte path trace message. ** B3 value depend on payload contents. *** G1 value depends on incoming path bit errors. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 49 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.14 Transmit ATM Cell Processor The Transmit ATM Cell Processor (TACP) provides rate adaptation via idle/unassigned cell insertion, provides HCS generation and insertion, and performs ATM cell scrambling. The TACP contains a four-cell transmit FIFO. An idle or unassigned cell is transmitted if a complete ATM cell has not been written into the FIFO. 9.14.1 Idle/Unassigned Cell Generator The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell stream when enabled. Registers are provided to program the GFC, PTI and CLP fields of the idle cell header and the idle cell payload. The idle cell HCS is automatically calculated and inserted. 9.14.2 Scrambler The Scrambler scrambles the 48-octet information field. Scrambling is performed using a parallel implementation of the self-synchronous scrambler described in the references. The cell headers are transmitted unscrambled, and the scrambler may optionally be completely disabled. 9.14.3 HCS Generator The HCS Generator performs a CRC-8 calculation over the first four header octets. A parallel implementation of the polynomial, x8+x2+x+1 is used. The coset polynomial, x6+x4+x2+1 is added (modulo 2) to the residue. The HCS Generator optionally inserts the result into the fifth octet of the header. 9.14.4 GFC Insertion Port The GFC Insertion Port provides the ability to insert the GFC value downstream of the FIFO. The four GFC bits are received on a serial stream that is synchronized to the transmit cell by a framing pulse. The GFC enable register bits control the insertion of each serial bit. If the enable is cleared, the default GFC value is inserted. For idle/unassigned cells, the default is the contents of the TACP Idle/Unassigned Cell Header Control register. For assigned cells, the default is the value written with the cell into the transmit FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 50 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 9.14.5 Transmit FIFO The Transmit FIFO provides FIFO management and the asynchronous interface between the S/UNI-622 device and the external environment. The transmit FIFO can accommodate four cells. It provides for the separation of the STS-12c/3c/1 line or physical layer timing from the ATM layer timing. The FIFO supports a data structure consists of twenty-seven 16-bit words consisting of the 5-octet cell header and the 48-octet payload (the HCS byte, along with the header error insertion control, is passed in this structure). Note that the header error insertion control allows the programmable insertion of one or more bit errors in the HCS octet. Management functions include filling the transmit FIFO, indicating when cells are available to be written to the transmit FIFO, maintaining the transmit FIFO read and write pointers, and detecting a FIFO overrun condition. The FIFO depth can be programmed to be from one to four cells deep. When configured for a depth of four cells, the TCA output signal transitions low to indicate a full FIFO when the FIFO contains four cells. To obtain maximum throughput with minimum FIFO latency, the FIFO level should be programmed to three cells. Note that a cell is not transmitted until the entire cell has been written into the FIFO. When the FIFO is full and the upstream device writes into the FIFO, the TACP622 indicates a FIFO overrun condition using a maskable interrupt and register bits. The offending write and all subsequent writes are ignored until there is room in the FIFO. The FIFO interface provided to the system is a synchronous interface emulating commercial synchronous FIFOs. All transmit FIFO signals, TSOC, TWRENB, TCA, TXPRTY[1:0] and TDAT[15:0] are either sampled or updated on the rising edge of the TFCLK clock input. 9.15 SONET/SDH Section and Path Trace Buffers The SONET/SDH Section Trace Buffer (SSTB) block and the SONET/SDH Path Trace Buffer (SPTB) block are identical. The blocks can handle both 64-byte CLLI messages in SONET and 16-byte E.164 messages in SDH. The generic SONET/SDH Trace Buffer (STB) block is described below. 9.15.1 Receive Trace Buffer (RTB) The RTB consists of two parts: the Trace Message Receiver and the Overhead Byte Receiver. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 51 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Trace Message Receiver: The Trace Message Receiver (TMR) processes the trace message, and consists of three sub-processes: Framer, Persistency, and Compare. Framer: The TMR handles the incoming 16-byte message by synchronizing to the byte with the most significant bit set high, and places that byte in the first location in the capture page of the internal RAM. In the case of the 64-byte message, the TMR synchronizes to the trailing carriage return (0x0D), line feed (0x0A) sequence and places the next byte in the first location in the capture page of the internal RAM. The Framer block maintains an internal representation of the resulting 16-byte or 64-byte "frame" cycle. If the phase of the start of frame shifts, the framer adjusts accordingly and resets the persistency counter and increments the unstable counter. Frame synchronization may be disabled, in which case the RAM acts as a circular buffer. Persistency: The Persistency process checks for repeated reception of the same 16-byte or 64-byte trace message. An unstable counter is incremented for each message that differs from the previous received message. For example, a single corrupted message in a field of constant messages causes the unstable count to increment twice, once on receipt of the corrupted message, and again on the next (uncorrupted) message. A section/path trace message unstable alarm is declared when the count reaches eight. The persistency counter is reset to zero, the unstable alarm is removed, and the trace message is accepted when the same 16-byte or 64-byte message is received three or five times consecutively (as determined by an internal register bit). The accepted message is passed to the Compare process for comparison with the expected message. Compare: A receive trace message mismatch alarm is declared if the accepted message (i.e., the message that passed the persistency check) does not match the expected message (previously downloaded to the receive expected page by the microprocessor). The mismatch alarm is removed if the accepted message is allzero, or if the accepted message is identical to the expected message. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 52 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Overhead Byte Receiver: The Overhead Byte Receiver (OBR) processes the path signal label byte (C2) and the synchronization status byte (Z1). The OBR consists of two subprocesses: Persistency and Compare. Persistency: The Persistency process checks for the repeated reception of the same C2 (Z1) byte. An unstable counter is incremented for each received C2 (Z1) byte that differs from the byte received in the previous frame. For example, a single corrupted byte value in a sequence of constant values causes the unstable count to increment twice, once on receipt of the corrupted value, and again on the next (uncorrupted) value. A path signal label unstable alarm or a synchronization status unstable alarm is declared when either unstable counter reaches five. The unstable counter is reset to zero, the unstable alarm is removed, and the byte value is accepted when the same label is received in five consecutive frames. The accepted value is passed to the Compare process for comparison with the expected value. Compare: A path signal label mismatch alarm or a synchronization status mismatch alarm is declared if the accepted C2 or Z1 byte (i.e., the byte value that has passed the persistency check) does not match the expected C2 or Z1 byte (previously downloaded by the microprocessor). The mismatch alarm is cleared when the accepted value matches the expected value. The receive path signal label mismatch mechanism follows the table below: Table 2 Expect 00 00 00 01 01 01 Receive 00 01 XX 00 01 XX Action Match Mismatch Mismatch Mismatch Match Match PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 53 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Expect XX XX XX XX Note: Receive 00 01 XX YY Action Mismatch Match Match Mismatch XX, YY = anything except 00H or 01H (XX not equal YY). 9.15.2 Transmit Trace Buffer (TTB) The TTB sources the 16-byte or 64-byte trace identifier message. The TTB contains one page of transmit trace identifier message memory. Identifier message data bytes are written by the microprocessor into the message buffer and inserted in the transmit stream. When the microprocessor is updating the transmit page buffer, the TTB may be programmed to transmit null characters to prevent transmission of partial messages. 9.16 Line Side Interface A byte-serial TTL-compatible receive and transmit line side interface is provided when configured for STS-12c (STM-4c), STS-3c (STM-1) or STS-1 operation. In addition, for STS-1 operation, a bit-serial interface is also supported. 9.16.1 Receive Interface The receive interface is either a generic byte-wide interface for interconnection with an upstream serial-to-parallel converter or a bit-serial interface for operation with an internal serial-to-parallel converter. When operating with the upstream serial-to-parallel converter, the upstream device is expected to provide data that is demultiplexed according to SONET/SDH byte boundaries along with a 77.76 MHz (STS-12c), 19.44 MHz (STS-3c) or 6.48 MHz (STS-1) clock. In addition, the upstream serial-to-parallel converter is expected to provide a framing pattern detector that performs part of the framing function. The serial-to-parallel converter need not perform descrambling as this is provided by the S/UNI-622. When enabled to search for frame alignment by the S/UNI-622 OOF output being high, the upstream device should realign to any occurrence of the SONET/SDH framing pattern and provide PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 54 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) an appropriate pulse on the S/UNI-622 FPIN input. The upstream device should ignore framing patterns and retain its byte alignment when the S/UNI-622 OOF output is low. When operating in STS-1 mode, the bit-serial interface can be used. An internal Serial-to-Parallel Converter (SIPO) block provides the first stage of digital processing of the receive incoming STS-1 bit-serial data stream. The byte alignment in the incoming stream is determined by searching for the 16-bit frame alignment signal (A1, A2). The bit-serial stream (RSIN) is converted from serial to parallel format in accordance with the determined byte alignment. In this mode of operation, the generated divide-by-eight clock output on GROCLK should be used to drive the input receive clock, PICLK. 9.16.2 Transmit Interface The transmit interface is either a generic byte-wide interface for interconnection with a downstream parallel-to-serial converter or a bit-serial interface for operation with an internal parallel-to-serial converter. When operating with the downstream parallel-to-serial converter, the S/UNI-622 device provides a byte-serial 77.76 Mbits/s (STS-12c), 19.44 Mbits/s (STS-3c) or 6.48 Mbits/s (STS-1) stream depending on the operating mode. The downstream serializer is expected to accept the transmit stream in byte-serial format and serializes it at the appropriate line rate. When operating in STS-1 mode, the bit-serial interface can be used. An internal Parallel-to-Serial Converter (PISO) block provides the final stage of digital processing for the transmit STS-1 data stream. The PISO block converts the data stream from parallel to serial format. In this mode of operation, the generated divide-by-eight clock output on GTOCLK should be used to drive the input transmit clock, TCLK. 9.17 Drop Side Interface 9.17.1 Receive Interface The drop side receive interface can be accessed through a generic 19-bit wide interface. External circuitry is notified, using the RCA signal, when a cell is available in the receive FIFO. External circuitry may then read the cell from the buffer as a word-wide stream (along with a bit marking the first word of the cell) at instantaneous rates up to 52 MHz. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 55 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) The cell data structure supported is described in the Receive ATM Cell Processor block description above. 9.17.2 Transmit Interface The drop side transmit interface can be accessed through a generic 19-bit wide interface. External circuitry is notified using the TCA signal when a cell may be written to the transmit FIFO. The cell is written to the FIFO as a word-wide stream (along with a bit marking the first word of the cell) at instantaneous rates of up to 52 MHz. The cell data structure supported is described in the Transmit ATM Cell Processor block description above. 9.18 Parallel I/O Port The Parallel Input/Output Port block provides six generic outputs and four generic inputs that can be used to control and monitor front end devices. Typical front end devices include parallel-to-serial conversion, serial-to-parallel conversion, clock and data recovery, and clock synthesis integrated circuits. 9.19 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-622 identification code is 053550CD hexadecimal. 9.20 Microprocessor Interface The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the S/UNI-622. The register set is accessed as follows: 9.21 Register Memory Map Table 3 Address 0x00 Register S/UNI-622 Master Reset and Identity / Load Performance Meters PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 56 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Address 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16-0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D Register S/UNI-622 Master Configuration S/UNI-622 Master Interrupt Status PISO Interrupt S/UNI-622 Master Control/Monitor S/UNI-622 Master Auto Alarm S/UNI-622 Parallel Output Port S/UNI-622 Parallel Input Port S/UNI-622 Parallel Input Port Value S/UNI-622 Parallel Input Port Enable S/UNI-622 Transmit C1 S/UNI-622 APS Control/Status S/UNI-622 Receive K1 S/UNI-622 Receive K2 S/UNI-622 Receive Z1 S/UNI-622 Transmit Z1 RSOP Control/Interrupt Enable RSOP Status/Interrupt Status RSOP Section BIP-8 LSB RSOP Section BIP-8 MSB TSOP Control TSOP Diagnostic TSOP Reserved RLOP Control/Status RLOP Interrupt Enable/Interrupt Status RLOP Line BIP-96/24/8 LSB RLOP Line BIP-96/24/8 RLOP Line BIP-96/24/8 MSB RLOP Line FEBE LSB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 57 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Address 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24-0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E-0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B Register RLOP Line FEBE RLOP Line FEBE MSB TLOP Control TLOP Diagnostic TLOP Transmit K1 TLOP Transmit K2 BIDX Reserved BIMX Reserved BIMX Reserved SSTB Control SSTB Status SSTB Indirect Address SSTB Indirect Data SSTB Expected Clock Synchronization Message SSTB Clock Synchronization Message Status SSTB Reserved RPOP Status/Control RPOP Interrupt Status RPOP Pointer Interrupt Status RPOP Interrupt Enable RPOP Pointer Interrupt Enable RPOP Pointer LSB RPOP Pointer MSB RPOP Path Signal Label RPOP Path BIP-8 LSB RPOP Path BIP-8 MSB RPOP Path FEBE LSB RPOP Path FEBE MSB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 58 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Address 0x3C 0x3D 0x3E-0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E-0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 Register RPOP RDI RPOP Ring Control RPOP Reserved TPOP Control/Diagnostic TPOP Pointer Control TPOP Reserved TPOP Current Pointer LSB TPOP Current Pointer MSB TPOP Arbitrary Pointer LSB TPOP Arbitrary Pointer MSB TPOP Path Trace TPOP Path Signal Label TPOP Path Status TPOP Path User Channel TPOP Path Growth #1 (Z3) TPOP Path Growth #2 (Z4) TPOP Path Growth #3 (Z5) TPOP Reserved RACP Control RACP Interrupt Status RACP Interrupt Enable/Control RACP Match Header Pattern RACP Match Header Mask RACP Correctable HCS Error Count (LSB) RACP Correctable HCS Error Count (MSB) RACP Uncorrectable HCS Error Count (LSB) RACP Uncorrectable HCS Error Count (MSB) RACP Receive Cell Counter (LSB) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 59 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Address 0x5A 0x5B 0x5C 0x5D-0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E-0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76-0x7F 0x80 0x81-0xFF Register RACP Receive Cell Counter RACP Receive Cell Counter (MSB) RACP GFC Control/Misc. Control RACP Reserved TACP Control/Status TACP Idle/Unassigned Cell Header Pattern TACP Idle/Unassigned Cell Payload Octet Pattern TACP FIFO Control TACP Transmit Cell Counter (LSB) TACP Transmit Cell Counter TACP Transmit Cell Counter (MSB) TACP Fixed Stuff / GFC SPTB Control SPTB Status SPTB Indirect Address SPTB Indirect Data SPTB Expected Path Signal Label SPTB Path Signal Label Status SPTB Reserved BERM Control* BERM Interrupt* BERM Line BIP Accumulation Period LSB* BERM Line BIP Accumulation Period MSB* BERM Line BIP Threshold LSB* BERM Line BIP Threshold MSB* Reserved S/UNI Master Test Reserved for Test PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 60 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) * Refer to the operations section for recommended settings PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 61 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 10 NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S/UNI-622. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[7]) is low. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the S/UNI-622 to determine the programming state of the block. 3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect S/UNI-622 operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-622 operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 62 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x00: S/UNI-622 Master Reset and Identity / Load Performance Meters Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R R R R R R R Function RESET TYPE[2] TYPE[1] TYPE[0] ID[3] ID[2] ID[1] ID[0] Default 0 0 0 1 0 0 0 0 This register allows the revision number of the S/UNI-622 to be read by software permitting graceful migration to newer, feature-enhanced versions of the S/UNI-622. In addition, writing to this register simultaneously loads all the performance meter registers in the RSOP RLOP RPOP RACP and TACP blocks. , , , ID[3:0]: The ID bits can be read to provide a binary S/UNI-622 revision number. TYPE[2:0]: The TYPE bits can be read to distinguish the S/UNI-622 from the other members of the S/UNI family of devices. RESET: The RESET bit allows the S/UNI-622 to be reset under software control. If the RESET bit is a logic one, the entire S/UNI-622 is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the S/UNI-622 out of reset. Holding the S/UNI-622 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Otherwise, the effect of a software reset is equivalent to that of a hardware reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 63 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x01: S/UNI-622 Master Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RMODE[1:0]: The RMODE[1:0] bits select the operation rate of the S/UNI-622's receive side. The default configuration selects STS-12c rate operation. Table 4 MODE STS-1 byte-serial STS-3c (STM-1) byte-serial STS-1 bit-serial STS-12c (STM-4c) byte-serial Type R/W R/W R/W R/W R/W R/W R/W R/W Function TPTBEN TSTBEN SDH_C1 FIXPTR TMODE[1] TMODE[0] RMODE[1] RMODE[0] Default 0 0 0 1 1 1 1 1 RMODE[1:0] 00 01 10 11 Note: Mode switching may require the switching of external clocks (PICLK, RSICLK). The mode switch must be performed cleanly such that no internal clock glitches are generated. The mode switch is accomplished cleanly by first switching the external clock source, then resetting the S/UNI-622, then programming the RMODE bits to select the desired rate. TMODE[1:0]: The TMODE[1:0] bits select the operation rate of the S/UNI-622's transmit side. The default configuration selects STS-12c rate operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 64 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Table 5 MODE STS-1 byte-serial STS-3c (STM-1) byte-serial STS-1 bit-serial STS-12c (STM-4c) byte-serial TMODE[1:0] 00 01 10 11 Note: Mode switching may require the switching of external clocks (TCLK, TSICLK). The mode switch must be performed cleanly such that no internal clock glitches are generated. The mode switch is accomplished cleanly by first switching the external clock source, then resetting the S/UNI-622, then programming the TMODE bits to select the desired rate. FIXPTR: The FIXPTR bit disables trasnsmit payload pointer adjustments. If the FIXPTR bit is a logic one, the transmit payload pointer is set at 522. If FIXPTR is a logic zero, the payload pointer is controlled by the contents of the TPOP Pointer Control register. SDH_C1 The SDH_C1 bit selects whether to insert SONET or SDH format C1 section overhead bytes into the transmit stream. When SDH_C1 is set high, SDH format C1 bytes are selected for insertion. For this case, all the C1 bytes are forced to the value programmed in the S/UNI-622 Transmit C1 register. When SDH_C1 is set low, SONET format C1 bytes are selected for insertion. For this case, the C1 bytes of a STS-N signal are numbered incrementally from 1 to N. When SDH_C1 is set high, the transmit section trace buffer enable bit, TSTBEN can be used to overwrite the first C1 byte of a STS-N signal. TSTBEN The TSTBEN bit controls whether the section trace message stored in the SSTB block is inserted into the transmit stream (i.e., the first C1 byte). When TSTBEN is set high and the SDH_C1 is set high, the message stored in the SSTB is inserted into the transmit stream. When TSTBEN is set low or SDH_C1 is set low, the section trace message is supplied by the TSOP block PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 65 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) or via the corresponding TTOH input. Overhead insertion via the serial overhead insertion inputs, TTOHEN and TTOH[4:1], takes precedence over insertion via the SSTB block. TPTBEN The TPTBEN bit controls whether the path trace message stored in the SPTB block is inserted into the transmit stream (i.e., the J1 byte). When TPTBEN is set high, the message stored in the SPTB is inserted into the transmit stream. When TPTBEN is set low, the path trace message is supplied by the TPOP block or via the corresponding TPOH input. Overhead insertion via the serial overhead insertion inputs, TPOHEN and TPOH, takes precedence over insertion via the SPTB block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 66 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x02: S/UNI-622 Master Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function S/UNII STBI Reserved TACPI RACPI RPOPI RLOPI RSOPI Default X X X X X X X X This register allows the source of an active interrupt to be identified down to the block level. Further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. RSOPI: The RSOPI bit is high when an interrupt request is active from the RSOP block. The RSOP interrupt sources are enabled in the RSOP Control/Interrupt Enable Register. RLOPI: The RLOPI bit is high when an interrupt request is active from the RLOP block. The RLOP interrupt sources are enabled in the RLOP Interrupt Enable/Status Register. RPOPI: The RPOPI bit is high when an interrupt request is active from the RPOP block. The RPOP interrupt sources are enabled in the RPOP Interrupt Enable Register. RACPI: The RACPI bit is high when an interrupt request is active from the RACP block. The RACP interrupt sources are enabled in the RACP Interrupt Enable/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 67 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) TACPI: The TACPI bit is high when an interrupt request is active from the TACP block. The TACP interrupt sources are enabled in the TACP Interrupt Control/Status Register. STBI: The STBI bit is high when an interrupt request is active from either the SSTB block or the SPTB block. The SSTB interrupt sources are enabled in the SSTB Control Register and the SSTB Clock Synchronization Message Status Register. The SPTB interrupt sources are enabled in the SPTB Control Register and the SPTB Path Signal Label Status Register. S/UNII: The S/UNII bit is high when an interrupt request is active from the Parallel Input/Output Block, the Z1 Change Block, the BERM Block, the PISO Block or the APS Block. The Parallel Input/Output interrupt sources are enabled in the S/UNI-622 Parallel Input Port Enable Register. The Z1 Change interrupt source and the APS interrupt sources are enabled in the S/UNI-622 APS Control/Status Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 68 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x03: PISO Interrupt Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAEI: The PAEI bit is set high when a phase alignment error occurs. This bit is cleared when the PISO Interrupt register is read. PAEE: The PAEE bit is an interrupt mask for phase alignment error events. When PAEE is a logic one, an interrupt is generated when a phase alignment error occurs. R/W R Type Function Unused Unused Unused Unused Unused Unused PAEE PAEI Default X X X X X X 0 X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 69 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x04: S/UNI-622 Master Control/Monitor Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R R Function TCAINV RCAINV LLE DLE LOOPT DPLE PICLKA TCLKA Default 0 0 0 0 0 0 X X This register provides polarity control for outputs RCA and TCA, STS-1 loopback control and activity monitoring on S/UNI-622 PICLK and TCLK clock inputs. TCLKA: The TCLK active (TCLKA) bit monitors activity on input TCLK to aid in the detection of a loss of clock state. When TCLK makes a low to high transition, the TCLKA bit is set high. The bit will remain high until this register is read at which point the TCLKA bit is cleared. Therefore, a lack of transitions on TCLK is indicated when TCLKA is low. This register should be read at periodic intervals to detect clock failures. PICLKA: The PICLK active (PICLKA) bit monitors activity on input PICLK to aid in the detection of a loss of clock state. When PICLK makes a low to high transition, the PICLKA bit is set high. The bit will remain high until this register is read at which point the PICLKA bit is cleared. Therefore, a lack of transitions on PICLK is indicated when PICLKA is low. This register should be read at periodic intervals to detect clock failures. DPLE: The Diagnostic Path Loopback, DPLE bit enables the S/UNI-622 diagnostic loopback where the S/UNI-622's Transmit Path Overhead Processor (TPOP) is directly connected to its Receive Path Overhead Processor (RPOP). When DPLE is logic one, loopback is enabled. Under this operating condition, the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 70 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) S/UNI-622 continues to operates normally in the transmit direction. When DPLE is logic zero, the S/UNI-622 operates normally. LOOPT: The LOOPT bit can only be used when configured for STS-1 bit-serial mode in both the transmit and receive directions. In STS-1 bit-serial mode, the LOOPT bit selects the source of timing for the transmit section of the S/UNI-622. When LOOPT is a logic zero, the transmitter timing is derived from input TSICLK. When LOOPT is a logic one, the transmitter timing is derived from receiver input RSICLK. DLE: The DLE bit can only be used when configured for STS-1 bit-serial mode in both the transmit and receive directions. The DLE bit enables the S/UNI-622 diagnostic loopback where the S/UNI-622 transmitter is looped back to the receiver. When DLE is a logic one, output TSOUT is connected internally to input RSIN. In addition, input clock TSICLK is used to replace RSICLK as the main receive clock. When DLE is logic zero, the S/UNI-622 operates normally. LLE: The LLE bit can only be used when configured for STS-1 bit-serial mode in both the transmit and receive directions. The LLE bit enables the S/UNI line loopback where the receive bit stream is sampled, retimed and immediately transmitted. When LLE is a logic one, input RSIN is connected internally to output TSOUT which is output with timing aligned to RSICLK. When LLE is logic zero, the S/UNI-622 operates normally. RCAINV: The RCAINV bits select the active polarity of the RCA signal. The default configuration selects RCA to be active high, indicating that a received cell is available when high. When RCAINV is set to logic one, the RCA signal becomes active low. If the state of the RCAINV bit has been changed, the receive FIFO must be reset via the FIFORST bit in the RACP Control register in order to properly initialize the RCA output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 71 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) TCAINV: The TCAINV bits select the active polarity of the TCA signal. The default configuration selects TCA to be active high, indicating that a cell is available in the transmit FIFO when high. When TCAINV is set to logic one, the TCA signal becomes active low. If the state of the TCAINV bit has been changed, the transmit FIFO must be reset via the FIFORST bit in the TACP Control/Status register in order to properly initialize the TCA output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 72 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x05: S/UNI-622 Master Auto Alarm Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOPRDI The AUTOPRDI bit determines whether the path remote defect indication is sent immediately upon detection of an incoming alarm. When AUTOPRDI is set to logic one, the path remote defect indication is inserted immediately upon declaration of loss of signal (LOS), loss of frame (LOF), line AIS, loss of pointer (LOP), or STS path AIS. AUTOLRDI The AUTOLRDI bit determines whether line remote defect indication (LRDI) is sent immediately upon detection of an incoming alarm. When AUTOLRDI is set to logic one, line RDI is inserted immediately upon declaration of loss of signal (LOS), loss of frame (LOF), or line AIS. AUTOFEBE The AUTOFEBE bit determines whether line and path far end block errors are sent upon detection of an incoming line and path BIP error events. When AUTOFEBE is set to logic one, one line or path FEBE is inserted for each line or path BIP error event. When AUTOFEBE is set to logic zero, incoming line or path BIP error events do not generate FEBE events. R/W R/W R/W Type Function Unused Unused Unused Unused Unused AUTOFEBE AUTOLRDI AUTOPRDI Default X X X X X 1 1 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 73 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x06: S/UNI-622 Parallel Output Port Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POP[5:0]: The values written to the POP[5:0] bit in the S/UNI-622 Parallel Output Port register directly correspond to the states set on the POP[5:0] output pins. This provides a generic port useful for controlling parallel-to-serial conversion devices, serial-to-parallel conversion devices, clock and data recovery devices or clock synthesis devices. The default states for this port are chosen so that POP[2:0] controls active-high signals while POP[5:3] controls activelow signals. R/W R/W R/W R/W R/W R/W Type Function Unused Unused POP[5] POP[4] POP[3] POP[2] POP[1] POP[0] Default X X 1 1 1 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 74 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x07: S/UNI-622 Parallel Input Port Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIPI[7:0]: The PIPI[7:0] bits are interrupt indications. A logic one in any bit location indicates that an event has occurred on the corresponding PIP[3:0] inputs. A logic one in any of the PIPI[7:4] bit locations indicates that the signal on the corresponding PIP[3:0] input has transitioned from logic zero to logic one (i.e., upon detection of a rising edge). A logic one in any of the PIPI[3:0] bit locations indicates that the signal on the corresponding PIP[3:0] input has transitioned either from logic zero to logic one or from logic one to logic zero (i.e., upon a change of state). The PIPI[7:0] bits are cleared by reading this register. These register bits function independently from the S/UNI-622 Parallel Input Port Enable register bits. The PIPI[7:0] bits will indicate events occurring on the PIP[3:0] inputs regardless of whether or not these events are enabled to generate an interrupt. The PIP[3:0] inputs are intended to monitor the frequency lock indications of the front end clock recovery and clock synthesis devices and one shot events like line code violations. Type R R R R R R R R Function PIPI[7] PIPI[6] PIPI[5] PIPI[4] PIPI[3] PIPI[2] PIPI[1] PIPI[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 75 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x08: S/UNI-622 Parallel Input Port Value Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIPV[3:0]: The PIPV[3:0] bits are real-time input port state indications. A logic one in any bit location indicates that the signal on the corresponding PIP[3:0] input is a logic one. A logic zero in any bit location indicates that the signal on the corresponding PIP[3:0] input is a logic zero. R R R R Type Function Unused Unused Unused Unused PIPV[3] PIPV[2] PIPV[1] PIPV[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 76 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x09: S/UNI-622 Parallel Input Port Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIPE[7:0]: The PIPE[7:0] bits are interrupt enables. When a logic one is written to these locations, the occurrence of an event indicated using the corresponding S/UNI-622 Parallel Input Port Register bit activates the interrupt, INTB. The interrupt is cleared by reading the S/UNI-622 Parallel Input Port Register. When a logic zero is written to these locations, the occurrence of an event as indicated in the S/UNI-622 Parallel Input Port Register is inhibited from activating the interrupt. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PIPE[7] PIPE[6] PIPE[5] PIPE[4] PIPE[3] PIPE[2] PIPE[1] PIPE[0] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 77 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x0A: S/UNI-622 Transmit C1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C1[7:0]: The value written to these bit positions is inserted into the C1 byte positions of the transmit stream when enabled using the SDH_C1 bit in the S/UNI-622 Master Configuration register. C1[7] is the most significant bit corresponding to bit 1, the first bit transmitted. C1[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. Insertion of the C1 byte via the serial overhead insertion inputs, TTOHEN and TTOH[4:1], takes precedence over insertion via the Transmit C1 register. Insertion of the section trace message (the first C1 byte when SDH_C1 is high) also takes precedence over C1 insertion via the Transmit C1 register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function C1[7] C1[6] C1[5] C1[4] C1[3] C1[2] C1[1] C1[0] Default 1 1 0 0 1 1 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 78 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x0B: S/UNI-622 APS Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PSBFV: The PSBFV bit indicates the protection switching byte failure alarm state. The alarm is declared (PSBFV is set high) when twelve successive frames, where no three consecutive frames contain identical K1 bytes, have been received. The alarm is removed (PSBFV is set low) when three consecutive frames containing identical K1 bytes have been received. COAPSI: The COAPSI bit is set high when a new APS code value has been extracted into the S/UNI-622 Receive K1/K2 Registers. The registers are updated when the same new K1/K2 byte values are observed for three consecutive frames. This bit is cleared when the S/UNI-622 APS Control/Status Register is read. PSBFI: The PSBFI bit is set high when the protection switching byte failure alarm is declared or removed. This bit is cleared when the S/UNI-622 APS Control/Status Register is read. Z1I: The Z1I bit is set high when a new Z1 byte value has been extracted into the S/UNI-622 Receive Z1 Register. The register is updated when a Z1 byte value is extracted that is different than the Z1 byte value extracted in the previous frame. This bit is cleared when the S/UNI-622 APS Control/Status Register is read. R Type R/W R/W R/W R R R Function PSBFE COAPSE Z1E Z1I PSBFI COAPSI Unused PSBFV Default 0 0 0 X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 79 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Z1E: The change of Z1 interrupt enable is an interrupt mask for changes in the receive Z1 byte value. When Z1E is a logic one, an interrupt is generated when the extracted Z1 byte is different from the Z1 byte extracted in the previous frame. COAPSE: The change of APS byte interrupt enable is an interrupt mask for events detected by the receive APS processor. When COAPSE is a logic one, an interrupt is generated when a new K1/K2 code value has been extracted into the S/UNI-622 Receive K1/K2 Registers. PSBFE: The change of protection switch byte failure alarm interrupt enable is an interrupt mask for events detected by the receive APS processor. When PSBFE is a logic one, an interrupt is generated upon a change in the protection switch byte failure alarm state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 80 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x0C: S/UNI-622 Receive K1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K1[7:0]: The K1[7:0] bits contain the current K1 code value. The contents of this register are updated when a new K1 code value (different from the current K1 code value) has been received for three consecutive frames. An interrupt may be generated when a new code value is received (using the COAPSE bit in the S/UNI-622 APS Control Register). K1[7] is the most significant bit corresponding to bit 1, the first bit received. K1[0] is the least significant bit, corresponding to bit 8, the last bit received. Type R R R R R R R R Function K1[7] K1[6] K1[5] K1[4] K1[3] K1[2] K1[1] K1[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 81 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x0D: S/UNI-622 Receive K2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K2[7:0]: The K2[7:0] bits contain the current K2 code value. The contents of this register are updated when a new K2 code value (different from the current K2 code value) has been received for three consecutive frames. An interrupt may be generated when a new code value is received (using the COAPSE bit in the S/UNI-622 APS Control Register). K2[7] is the most significant bit corresponding to bit 1, the first bit received. K2[0] is the least significant bit, corresponding to bit 8, the last bit received. Type R R R R R R R R Function K2[7] K2[6] K2[5] K2[4] K2[3] K2[2] K2[1] K2[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 82 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x0E: S/UNI-622 Receive Z1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z1[7:0]: The first Z1 byte contained in the receive stream is extracted into this register. The Z1 byte is used to carry synchronization status messages between line terminating network elements. Z1[7] is the most significant bit corresponding to bit 1, the first bit received. Z1[0] is the least significant bit, corresponding to bit 8, the last bit received. An interrupt may be generated when a byte value is received that differs from the value extracted in the previous frame using the Z1E bit in the APS Control/Status Register. Type R R R R R R R R Function Z1[7] Z1[6] Z1[5] Z1[4] Z1[3] Z1[2] Z1[1] Z1[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 83 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x0F: S/UNI-622 Transmit Z1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z1[7:0]: The value written to these bit positions is inserted in the first Z1 byte position of the transmit stream. The Z1 byte is used to carry synchronization status messages between line terminating network elements. Z1[7] is the most significant bit corresponding to bit 1, the first bit transmitted. Z1[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. Insertion of the Z1 byte via the serial transport overhead insertion inputs TTOHEN and TTOH[1] takes prececence over Z1 insertion via the S/UNI-622 Transmit Z1 register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z1[7] Z1[6] Z1[5] Z1[4] Z1[3] Z1[2] Z1[1] Z1[0] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 84 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x10: RSOP Control/Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFE: The OOFE bit is an interrupt enable for the out-of-frame alarm. When OOFE is set to logic one, an interrupt is generated when the out-of-frame alarm changes state. LOFE: The LOFE bit is an interrupt enable for the loss of frame alarm. When LOFE is set to logic one, an interrupt is generated when the loss of frame alarm changes state. LOSE: The LOSE bit is an interrupt enable for the loss of signal alarm. When LOSE is set to logic one, an interrupt is generated when the loss of signal alarm changes state. BIPEE: The BIPEE bit is an interrupt enable for the section BIP-8 errors. When BIPEE is set to logic one, an interrupt is generated when a section BIP-8 error (B1) is detected. ALGO2: The ALGO2 bit position selects the framing algorithm used to determine and maintain the frame alignment. When a logic one is written to the ALGO2 bit position, the framer is enabled to use the second of the framing algorithms where only the first A1 framing byte and the first 4 bits of the first A2 framing Type R/W R/W W R/W R/W R/W R/W R/W Function BIPWORD DDS FOOF ALGO2 BIPEE LOSE LOFE OOFE Default 0 0 X 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 85 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) byte (12 bits total) are examined. This algorithm examines only 12 bits of the framing pattern regardless; all other framing bits are ignored. When a logic zero is written to the ALGO2 bit position, the framer is enabled to use the first of the framing algorithms where all the A1 framing bytes and all the A2 framing bytes are examined. FOOF: The FOOF bit controls the framing of the RSOP When a logic one is written . to FOOF, the RSOP is forced out of frame at the next frame boundary. The FOOF bit is a write only bit, register reads may yield a logic one or a logic zero. DDS: The DDS bit is set to logic one to disable the descrambling of the STS-12c/3c/1 stream. When DDS is a logic zero, descrambling is enabled. BIPWORD: The BIPWORD bit position enables the reporting and accumulating of section BIP word errors. When a logic one is written to the BIPWORD bit position, one or more errors in the BIP-8 byte result in a single error being accumulated in the B1 error counter. When a logic zero is written to the BIPWORD bit position, all errors in the B1 byte are accumulated in the B1 error counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 86 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x11: RSOP Status/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFV: The OOFV bit is read to determine the out-of-frame state of the RSOP When . OOFV is high, the RSOP is out of frame. When OOFV is low, the RSOP is in-frame. LOFV: The LOFV bit is read to determine the loss of frame state of the RSOP When . LOFV is high, the RSOP has declared loss of frame. LOSV: The LOSV bit is read to determine the loss of signal state of the RSOP When . LOSV is high, the RSOP has declared loss of signal. OOFI: The OOFI bit is the out-of-frame interrupt status bit. OOFI is set high when a change in the out-of-frame state occurs. This bit is cleared when this register is read. LOFI: The LOFI bit is the loss of frame interrupt status bit. LOFI is set high when a change in the loss of frame state occurs. This bit is cleared when this register is read. R R R R R R R Type Function Unused BIPEI LOSI LOFI OOFI LOSV LOFV OOFV Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 87 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) LOSI: The LOSI bit is the loss of signal interrupt status bit. LOSI is set high when a change in the loss of signal state occurs. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is set high when a section layer (B1) bit error is detected. This bit is cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 88 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x12: RSOP Section BIP-8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function SBE[7] SBE[6] SBE[5] SBE[4] SBE[3] SBE[2] SBE[1] SBE[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 89 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x13: RSOP Section BIP-8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBE[15:0]: Bits SBE[15:0] represent the number of section BIP-8 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RSOP Section BIP-8 Register addresses. Such a write transfers the internally accumulated error count to the Section BIP-8 registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. Type R R R R R R R R Function SBE[15] SBE[14] SBE[13] SBE[12] SBE[11] SBE[10] SBE[9] SBE[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 90 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x14: TSOP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LAIS: The LAIS bit controls the insertion of line alarm indication signal (AIS). When LAIS is set to logic one, the TSOP inserts AIS into the transmit SONET stream. Activation or deactivation of line AIS insertion is synchronized to frame boundaries. Line AIS insertion results in all bits of the SONET frame being set to 1 prior to scrambling except for the section overhead. The LAIS bit is logically ORed with the external TLAIS input. DS: The DS bit is set to logic one to disable the scrambling of the STS-12c/3c/1 stream. When DS is a logic zero, scrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R/W R/W R/W R/W R/W Type Function Unused DS Reserved Reserved Reserved Reserved Reserved LAIS Default X 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 91 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x15: TSOP Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DFP: The DFP bit controls the insertion of a single bit error continuously in the most significant bit (bit 1) of the A1 section overhead framing byte. When DFP is set to logic one, the A1 bytes are set to 0x76 instead of 0xF6. DBIP8: The DBIP8 bit controls the insertion of bit errors continuously in the section BIP-8 byte (B1). When DBIP8 is set to logic one, the B1 byte is inverted. DLOS: The DLOS bit controls the insertion of all zeros in the STS-12c/3c/1 stream. When DLOS is set to logic one, the transmit stream is forced to 0x00. R/W R/W R/W Type Function Unused Unused Unused Unused Unused DLOS DBIP8 DFP Default X X X X X 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 92 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x18: RLOP Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDIV: The LRDIV bit is read to determine the remote defect indication state of the RLOP When LRDIV is high, the RLOP has declared line RDI. . LAISV: The LAISV bit is read to determine the line AIS state of the RLOP When . LAISV is high, the RLOP has declared line AIS. BIPWORDO: The BIPWORDO bit controls the indication of B2 errors reported to the TLOP block for insertion as FEBEs. When BIPWORDO is logic one, the BIP errors are indicated once per frame whenever one or more B2 bit errors occur during that frame. When BIPWORDO is logic zero, BIP errors are indicated once for every B2 bit error that occurs during that frame. The accumulation of B2 error events functions independently and is controlled by the BIPWORD register bit. LRDIDET: The LRDIDET bit determines the line RDI alarm detection algorithm. When LRDIDET is set to logic one, line RDI is declared when a 110 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for three consecutive frames. When LRDIDET is set to logic zero, line RDI is declared when a 110 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for five consecutive frames. R R Type R/W R/W R/W R/W R/W Function BIPWORD ALLONES AISDET LRDIDET BIPWORDO Unused LAISV LRDIV Default 0 0 0 0 0 X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 93 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) AISDET: The AISDET bit determines the line AIS alarm detection algorithm. When AISDET is set to logic one, line AIS is declared when a 111 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for three consecutive frames. When AISDET is set to logic zero, line AIS is declared when a 111 binary pattern is detected in bits 6, 7 and 8 of the K2 byte for five consecutive frames. ALLONES: The ALLONES bit controls automatically forcing the SONET frame passed to downstream blocks to logical all-ones whenever line AIS is detected. When ALLONES is set to logic one, the SONET frame is forced to logic one immediately when the line AIS alarm is declared. When line AIS is removed, the outputs are immediately returned to carrying the data sampled on PIN[7:0]. When ALLONES is set to logic zero, the outputs carry the data sampled on PIN[7:0] regardless of the state of the line AIS alarm. BIPWORD: The BIPWORD bit controls the accumulation of B2 errors. When BIPWORD is logic one, the B2 error event counter is incremented only once per frame whenever one or more B2 bit errors occur during that frame. When BIPWORD is logic zero, the B2 error event counter is increment for each and every B2 bit error that occurs during that frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 94 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x19: RLOP Interrupt Enable/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDII: The LRDII bit is the remote defect indication interrupt status bit. LRDII is set high when a change in the line RDI state occurs. This bit is cleared when this register is read. LAISI: The LAISI bit is the line AIS interrupt status bit. LAISI is set high when a change in the line AIS state occurs. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the line BIP-96/24/8 interrupt status bit. BIPEI is set high when a line layer (B2) bit error is detected. This bit is cleared when this register is read. FEBEI: The FEBEI bit is the line far end block error interrupt status bit. FEBEI is set high when a line layer FEBE (Z2) is detected. This bit is cleared when this register is read. LRDIE: The LRDIE bit is an interrupt enable for the line remote defect indication alarm. When LRDIE is set to logic one, an interrupt is generated when the line RDI state changes. Type R/W R/W R/W R/W R R R R Function FEBEE BIPEE LAISE LRDIE FEBEI BIPEI LAISI LRDII Default 0 0 0 0 X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 95 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) LAISE: The LAISE bit is an interrupt enable for line AIS. When LAISE is set to logic one, an interrupt is generated when line AIS changes state. BIPEE: The BIPEE bit is an interrupt enable for the line BIP-96/24/8 errors. When BIPEE is set to logic one, an interrupt is generated when a line BIP-96/24/8 error (B2) is detected. FEBEE: The FEBEE bit is an interrupt enable for the line far end block errors. When FEBE (Z2) is detected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 96 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x1A: RLOP Line BIP-96/24/8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LBE[7] LBE[6] LBE[5] LBE[4] LBE[3] LBE[2] LBE[1] LBE[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 97 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x1B: RLOP Line BIP-96/24/8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LBE[15] LBE[14] LBE[13] LBE[12] LBE[11] LBE[10] LBE[9] LBE[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 98 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x1C: RLOP Line BIP-96/24/8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LBE[19:0] Bits LBE[19:0] represent the number of line BIP-96/24/8 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to any of the RLOP Line BIP-96/24/8 Register or Line FEBE Register addresses. Such a write transfers the internally accumulated error count to the Line BIP-96/24/8 Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused LBE[19] LBE[18] LBE[17] LBE[16] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 99 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x1D: RLOP Line FEBE LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LFE[7] LFE[6] LFE[5] LFE[4] LFE[3] LFE[2] LFE[1] LFE[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 100 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x1E: RLOP Line FEBE Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LFE[15] LFE[14] LFE[13] LFE[12] LFE[11] LFE[10] LFE[9] LFE[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 101 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x1F: RLOP Line FEBE MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFE[19:0] Bits LFE[19:0] represent the number of line FEBE errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to any of the RLOP Line BIP-96/24/8 Register or Line FEBE Register addresses. Such a write transfers the internally accumulated error count to the Line FEBE Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused LFE[19] LFE[18] LFE[17] LFE[16] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 102 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x20: TLOP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDI: The LRDI bit controls the insertion of line remote defect indication (LRDI). When LRDI is set to logic one, the TLOP inserts line RDI into the transmit SONET stream. Line RDI is inserted by transmitting the code 110 in bit positions 6, 7 and 8 of the K2 byte of the STS-12c/3c/1 stream. The LRDI bit is logically ORed with the external TLRDI input. APSREG: The APSREG bit selects the source for the transmit APS channel. When APSREG is a logic zero, 0x0000 is inserted in the transmit APS channel. When APSREG is a logic one, the transmit APS channel is inserted from the TLOP Transmit K1 Register and the TLOP Transmit K2 Register. The APS bytes may also be inserted upstream of the TLOP using the TTOHEN and TTOH[4:1] inputs. Values inserted using the TTOHEN input take precedence over the source selected by the APSREG bit. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R/W R/W R/W R/W R/W Type Function Unused Reserved APSREG Reserved Reserved Reserved Reserved LRDI Default X 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 103 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x21: TLOP Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBIP96/24/8: The DBIP96/24/8 bit controls the insertion of bit errors continuously in the line BIP-96/24/8 bytes (B2). When DBIP96/24/8 is set to logic one, the B2 bytes are inverted. R/W Type Function Unused Unused Unused Unused Unused Unused Unused DBIP96/24/8 Default X X X X X X X 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 104 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x22: TLOP Transmit K1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K1[7:0]: The K1[7:0] bits contain the value inserted in the K1 byte when the APSREG bit in the TLOP Control Register is logic one. K1[7] is the most significant bit corresponding to bit 1, the first bit transmitted. K1[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. The bits in this register are double buffered so that register writes do not need to be synchronized to SONET/SDH frame boundaries. The insertion of a new APS code value is initiated by a write to this register. The contents of this register, and the TLOP Transmit K2 Register are inserted in the SONET/SDH stream starting at the next frame boundary. Successive writes to this register must be spaced at least two frames (250 s) apart. Type R/W R/W R/W R/W R/W R/W R/W R/W Function K1[7] K1[6] K1[5] K1[4] K1[3] K1[2] K1[1] K1[0] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 105 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x23: TLOP Transmit K2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K2[7:0]: The K2[7:0] bits contain the value inserted in the K2 byte when the APSREG bit in the TLOP Control Register is logic one. K2[7] is the most significant bit corresponding to bit 1, the first bit transmitted. K2[0] is the least significant bit, corresponding to bit 8, the last bit transmitted. The bits in this register are double buffered so that register writes do not need to be synchronized to SONET/SDH frame boundaries. The insertion of a new APS code value is initiated by a write to the TLOP Transmit K1 Register. A coherent APS code value is ensured by writing the desired K2 APS code value to this register before writing the TLOP Transmit K1 Register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function K2[7] K2[6] K2[5] K2[4] K2[3] K2[2] K2[1] K2[0] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 106 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x28 SSTB Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused RRAMACC RTIUIE RTIMIE PER5 TNULL NOSYNC LEN16 Default X 0 0 0 0 1 0 0 This register controls the receive and transmit portions of the SSTB. LEN16: The section trace message length bit (LEN16) selects the length of the section trace message to be 16 bytes or 64 bytes. When set high, a 16-byte section trace message is selected. If set low, a 64-byte section trace message is selected. NOSYNC: The section trace message synchronization disable bit (NOSYNC) disables the writing of the section trace message into the trace buffer to be synchronized to the content of the message. When LEN16 is set high and NOSYNC is set low, the receive section trace message byte with its most significant bit set will be written to the first location in the buffer. When LEN16 is set low, and NOSYNC is also set low, the byte after the carriage return/linefeed (CR/LF) sequence will be written to the first location in the buffer. When NOSYNC is set high, synchronization is disabled, and the section trace message buffer behaves as a circular buffer. TNULL: The transmit null bit (TNULL) controls the insertion of an all-zeros section trace identifier message in the transmit stream. When TNULL is set high, the contents of the transmit buffer is ignored and all-zeros bytes are provided to the TSOP block. When TNULL is set low the contents of the transmit section trace buffer is sent to TSOP for insertion into the C1 transmit section PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 107 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) overhead byte. TNULL should be set high before changing the contents of the trace buffer to avoid sending partial messages. PER5: The receive trace identifier persistence bit (PER5) control the number of times a section trace identifier message must be received unchanged before being accepted. When PER5 is set high, a message is accepted when it is received unchanged five times consecutively. When PER5 is set low, the message is accepted after three identical repetitions. RTIMIE: The receive section trace identifier message mismatch interrupt enable bit (RTIMIE) controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state from match to mismatch and vice versa. When RTIMIE is set high, changes in match state activates the interrupt (INTB) output. When RTIMIE is set low, section trace identifier message state changes will not affect INTB. RTIUIE: The receive section trace identifier message unstable interrupt enable bit (RTIUIE) controls the activation of the interrupt output when the receive identifier message state changes from stable to unstable and vice versa. The unstable state is entered when the current identifier message differs from the previous message for six consecutive messages. The stable state is entered when the same identifier message is received for three or five consecutive messages as controlled by the PER5 bit. When RTIUIE is set high, changes in the received section trace identifier message stable/unstable state of will activate the interrupt (INTB) output. When RTIUIE is set low, section trace identifier state changes will not affect INTB. RRAMACC: The receive RAM access control bit (RRAMACC) directs read and writes access to between the receive and transmit portion of the S/UNI-622. When RRAMACC is set high, subsequent microprocessor read and write accesses are directed to the receive side trace buffers. When RRAMACC is set low, microprocessor accesses are directed to the transmit side trace buffer. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 108 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x29: SSTB Section Trace Identifier Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R Function BUSY Unused Unused Unused RTIUI RTIUV RTIMI RTIMV Default 0 X X X X X X X This register reports the section trace identifier status of the SSTB. RTIMV: The receive section trace identifier message mismatch status bit (RTIMV) reports the match/mismatch status of the identifier message framer. RTIMV is set high when the accepted identifier message differs from the expected message written by the microprocessor. RTIMV is set low when the accepted message matches the expected message. RTIMI: The receive section trace identifier mismatch interrupt status bit (RTIMI) is set high when match/mismatch status of the trace identifier framer changes state. This bit and the interrupt are cleared when this register is read. RTIUV: The receive section trace identifier message unstable status bit (RTIUV) reports the stable/unstable status of the identifier message framer. RTIUV is set high when the current received section trace identifier message has not matched the previous message for eight consecutive messages. RTIUV is set low when the current message becomes the accepted message as determined by the PER5 bit in the SSTB Control register. RTIUI: The receive section trace identifier message unstable interrupt status bit (RTIUI) is set high when stable/unstable status of the trace identifier framer PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 109 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) changes state. This bit and the interrupt are cleared when this register is read. BUSY: The BUSY bit reports whether a previously initiated indirect read or write to a message buffer has been completed. BUSY is set high upon writing to the SSTB Indirect Address register, and stays high until the initiated access has completed. At which point, BUSY is set low. This register should be polled to determine when new data is available in the SSTB Indirect Data register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 110 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x2A: SSTB Indirect Address Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0] Default 0 0 0 0 0 0 0 0 This register supplies the address used to index into section trace identifier buffers. A[6:0]: The indirect read address bits (A[6:0]) indexes into the section trace identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference the receive capture page while addresses 64 to 127 reference the receive expected page. The receive capture page contains the identifier bytes extracted from the receive stream. The receive expected page contains the expected trace identifier message downloaded from the microprocessor. When RRAMACC is set low, addresses 0 to 63 reference the transmit message buffer which contains the identifier message to be inserted in the section trace byte, the first C1 byte, of each frame in the transmit stream. When RRAMACC is set low, addresses 64 to 127 are unused and must not be accessed. RWB: The access control bit (RWB) selects between an indirect read or write access to the static page of the section trace message buffer. Writing to this register initiates an external microprocessor access to the static page of the section trace message buffer. When RWB is set high, a read access is initiated. The data read can be found in the SSTB Indirect Data register. When RWB is set low, a write access is initiated. The data in the SSTB Indirect Data register will be written to the addressed location in the static page. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 111 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x2B: SSTB Indirect Data Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default 0 0 0 0 0 0 0 0 This register contains the data read from the section trace message buffer after a read operation or the data to be written into the buffer before a write operation. D[7:0]: The indirect data bits (D[7:0]) reports the data read from a message buffer after an indirect read operation has completed. The data to be written to a buffer must be set up in this register before initiating an indirect write operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 112 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x2C: SSTB Expected Clock Synchronization Message Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EZ1[7] EZ1[6] EZ1[5] EZ1[4] EZ1[3] EZ1[2] EZ1[1] EZ1[0] Default 0 0 0 0 0 0 0 0 This register contains the expected clock synchronization message byte (Z1) in the receive stream. EZ1[7:0]: The EZ1[7] - EZ1[0] bits contain the expected clock synchronization message byte (Z1). EZ1[7:0] is compared with the clock synchronization message byte extracted from the receive stream. A clock synchronization message byte mismatch (CSMM) is declared if the accepted clock synchronization message byte differs from the expected clock synchronization message byte. If enabled, an interrupt is asserted upon declaration and removal of CSMM. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 113 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x2D: SSTB Clock Synchronization Message Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R/W R/W Function RCSMUIE RCSMMIE Unused Unused RCSMUI RCSMUV RCSMMI RCSMMV Default 0 0 X X X X X X This register reports the clock synchronization message status of the SSTB. RCSMMV: The receive clock synchronization message mismatch status bit (RCSMMV) reports the match/mismatch status between the expected and the accepted clock synchronization message. RCSMMV is set high when the accepted CSM differs from the expected CSM written by the microprocessor. CSMMV is set low when the accepted CSM matches the expected CSM. RCSMMI: The receive clock synchronization message mismatch interrupt status bit (RCSMMI) is set high when the match/mismatch status between the accepted and the expected clock synchronization message changes state. This bit (and the interrupt) are cleared when this register is read. RCSMUV: The receive clock synchronization message unstable status bit (RCSMUV) reports the stable/unstable status of the clock synchronization message in the receive stream. RCSMUV is set high when the current received Z1 byte differs from the previous Z1 byte for five consecutive frames. RCSMUV is set low when the same CSM code is received for five consecutive frames. RCSMUI: The receive clock synchronization message unstable interrupt status bit (RCSMUI) is set high when the stable/unstable status of the clock PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 114 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) synchronization message changes state. This bit and the interrupt are cleared when this register is read. RCSMMIE: The receive clock synchronization message mismatch interrupt enable bit (RCSMMIE) controls the activation of the interrupt output when the comparison between accepted and the expected clock synchronization message changes state from match to mismatch and vice versa. When RCSMMIE is set high, changes in match state activates the interrupt (INTB) output. When RCSMMIE is set low, clock synchronization message state changes will not affect INTB. RCSMUIE: The receive clock synchronization message unstable interrupt enable bit (RCSMUIE) controls the activation of the interrupt output when the received clock synchronization message changes state from stable to unstable and vice versa. When RCSMUIE is set high, changes in stable state activates the interrupt (INTB) output. When RCSMUIE is set low, clock synchronization message state changes will not affect INTB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 115 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x30: RPOP Status/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R Type R/W Function Reserved Unused LOP Unused PAIS PRDI NEWPTRI NEWPTRE Default 0 X X X X X X 0 This register allows the status of path level alarms to be monitored. NEWPTRE: When a 1 is written to the NEWPTRE interrupt enable bit position, the reception of a new_point indication will activate the interrupt output. NEWPTRI: The NEWPTRI bit is set to logic one upon the reception of a new_pointer indication. PRDI, PAIS LOP: The PRDI, PAIS and LOP bits reflect the current state of the corresponding path level alarms. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 116 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x31: RPOP Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R Type R Function PSLI Unused LOPI Unused PAISI PRDII BIPEI FEBEI Default X X X X X X X X This register allows identification and acknowledgment of path level alarm and error event interrupts. FEBEI, BIPEI: The BIPEI and FEBEI bits are set to logic one when the corresponding event, a path BIP-8 error or path FEBE is detected. PRDII: The PRDII bit is set to logic one when a change is detected in the path remote defect indication or the auxiliary path remote defect indication bits. PAISI, LOPI: The PAISI, and LOPI bits are set to logic one when a transition occurs in the corresponding alarm state. PSLI: The PSLI bit is set to logic one when a change is detected in the path signal label register. The current path signal label can be read from the RPOP Path Signal Label register. All bits in this register (and the interrupt) are cleared when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 117 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x32: RPOP Pointer Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R Type R Function ILLJREQI Unused DISCOPAI INVNDFI ILLPTRI NSEI PSEI NDFI Default X X X X X X X X This register allows identification and acknowledgment of pointer event interrupts. NDFI: The NDFI bit is set to logic one when the RPOP detects an active NDF event to a valid pointer value. NDFI is cleared when the RPOP Pointer Interrupt Status register is read. PSEI: The PSEI bit is set to logic one when the RPOP detects a positive stuff event. PSEI is cleared when the RPOP Pointer Interrupt Status register is read. NSEI: The NSEI bit is set to logic one when the RPOP detects a negative stuff event. NSEI is cleared when the RPOP Pointer Interrupt Status register is read. ILLPTRI: The ILLPTRI bit is set to logic one when the RPOP detects an illegal pointer event. ILLPTRI is cleared when the RPOP Pointer Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 118 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) INVNDFI: The INVNDFI bit is set to logic one when the RPOP detects an invalid NDF event. INVNDFI is cleared when the RPOP Pointer Interrupt Status register is read. DISCOPAI: The DISCOPAI bit is set to logic one when the RPOP detects a discontinuous change of pointer. DISCOPAI is cleared when the RPOP Pointer Interrupt Status register is read. ILLJREQI: The ILLJREQI bit is set to logic one when the RPOP detects an illegal pointer justification request event. ILLJREQI is cleared when the RPOP Pointer Interrupt Status register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 119 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x33: RPOP Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PSLE Reserved LOPE Reserved PAISE PRDIE BIPEE FEBEE Default 0 0 0 0 0 0 0 0 This register allows interrupt generation to be enabled for path level alarm and error events. FEBEE: When a logic one is written to the FEBEE interrupt enable bit position, the reception of one or more FEBEs will activate the interrupt output. BIPEE: When a logic one is written to the BIPEE interrupt enable bit position, the detection of one or more path BIP-8 errors will activate the interrupt output. PRDIE: When a logic one is written to the PRDIE interrupt enable bit position, a change in the path remote defect indication state will activate the interrupt output. PAISE: When a logic one is written to the PAISE interrupt enable bit position, a change in the path AIS state will activate the interrupt output. LOPE: When a logic one is written to the LOPE interrupt enable bit position, a change in the loss of pointer state will activate the interrupt output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 120 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) PSLE: When a logic one is written to the PSLE interrupt enable bit position, a change in the path signal label will activate the interrupt output. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 121 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x34: RPOP Pointer Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ILLJREQE Reserved DISCOPAE INVNDFE ILLPTRE NSEE PSEE NDFE Default 0 0 0 0 0 0 0 0 This register is used to enable pointer event interrupts. NDFE: When a logic one is written to the NDFE interrupt enable bit position, a change in active offset due to the reception of an enabled NDF (NDF_enabled indication) will activate the interrupt output, INTB. PSEE: When a logic one is written to the PSEE interrupt enable bit position, a positive pointer adjustment event will activate the interrupt output, INTB. NSEE: When a logic one is written to the NSEE interrupt enable bit position, a negative pointer adjustment event will activate the interrupt output, INTB. ILLPTRE: When a logic one is written to the ILLPTRE interrupt enable bit position, an illegal pointer will activate the interrupt output, INTB. INVNDFE: When a logic one is written to the INVNDFE interrupt enable bit position, an invalid NDF code will activate the interrupt output, INTB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 122 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) DISCOPAE: When a logic one is written to the DISCOPAE interrupt enable bit position, a change of pointer alignment event will activate the interrupt output, INTB. ILLJREQE: When a logic one is written to the ILLJREQE interrupt enable bit position, an illegal pointer justification request will activate the interrupt output, INTB. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 123 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x35: RPOP Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTR[7:0]: The PTR[7:0] bits contain the eight LSBs of the current pointer value as derived from the H1 and H2 bytes. To ensure reading a valid pointer, the NDFI, NSEI and PSEI bits of the RPOP Pointer Interrupt Status register should be read before and after reading this register to ensure that the pointer value did not changed during the register read. Type R R R R R R R R Function PTR[7] PTR[6] PTR[5] PTR[4] PTR[3] PTR[2] PTR[1] PTR[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 124 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x36: RPOP Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTR[9:8]: The PTR[9:8] bits contain the two MSBs of the current pointer value as derived from the H1 and H2 bytes. Thus, to ensure reading a valid pointer, the NDFI, NSEI and PSEI bits of the RPOP Pointer Interrupt Status register should be read before and after reading this register to ensure that the pointer value did not changed during the register read. S0, S1: The S0 and S1 bits contain the two S bits received in the last H1 byte. These bits should be software debounced. RDI10: The RDI10 bit controls the filtering of the remote defect indication and the auxiliary remote defect indication. When RDI10 is set to logic one, the PRDI and ARDI statuses are updated when the same value is received in the corresponding bit of the G1 byte for 10 consecutive frames. When PRDI10 is set to logic zero, the PRDI and ARDI statuses are updated when the same value is received for 5 consecutive frames. R R R R R/W Type Function Unused Unused RDI10 Unused S1 S0 PTR[9] PTR[8] Default X X 0 X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 125 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x37: RPOP Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PSL[7:0]: The PSL[7:0] bits contain the path signal label byte (C2). The value in this register is updated to a new path signal label value if the same new value is observed for two consecutive frames. Type R R R R R R R R Function PSL[7] PSL[6] PSL[5] PSL[4] PSL[3] PSL[2] PSL[1] PSL[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 126 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x38: RPOP Path BIP-8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PBE[7] PBE[6] PBE[5] PBE[4] PBE[3] PBE[2] PBE[1] PBE[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 127 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x39: RPOP Path BIP-8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PBE[15] PBE[14] PBE[13] PBE[12] PBE[11] PBE[10] PBE[9] PBE[8] Default X X X X X X X X These registers allow path BIP-8 errors to be accumulated. PBE[15:0]: Bits PBE[15:0] represent the number of path BIP-8 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register addresses. Such a write transfers the internally accumulated error count to the Path BIP-8 Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 128 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x3A: RPOP Path FEBE LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PFE[7] PFE[6] PFE[5] PFE[4] PFE[3] PFE[2] PFE[1] PFE[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 129 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x3B: RPOP Path FEBE MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PFE[15] PFE[14] PFE[13] PFE[12] PFE[11] PFE[10] PFE[9] PFE[8] Default X X X X X X X X These registers allow path FEBEs to be accumulated. PFE[15:0]: Bits PFE[15:0] represent the number of path FEBE errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register addresses. Such a write transfers the internally accumulated error count to the Path FEBE Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 130 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x3C: RPOP RDI Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ARDIV: The auxiliary RDI bit (ARDIV) reports the current state of the path auxiliary RDI within the receive path overhead processor. ARDIE: When a 1 is written to the ARDIE interrupt enable bit position, a change in the path auxiliary RDI state will activate the interrupt (INTB) output. BLKFEBE: When set high, the block FEBE bit (BLKFEBE) causes path FEBE errors to be reported and accumulated on a block basis. A single path FEBE error is accumulated for a block if the received FEBE code for that block is between 1 and 8 inclusive. When BLKFEBE is set low, path FEBE errors are accumulated on a error basis. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R R/W R/W Type Function Unused Unused Reserved BLKFEBE Unused Reserved ARDIE ARDIV Default X X 0 0 X 0 0 X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 131 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x3D: RPOP Ring Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SOS ENSS BLKBIP DISFS BLKBIPO Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 This register contains ring control bits. BLKBIPO: When set high, the block BIP-8 output bit (BLKBIPO) indicates that path BIP-8 errors are to be reported on a block basis to the transmit path overhead processor, TPOP block. A single path BIP error is reported to the return , transmit path overhead processor if any of the path BIP-8 results indicates a mismatch. When BLKBIP is set low, BIP-8 errors are reported on a bit basis. DISFS: When set high, the DISFS bit controls the BIP-8 calculations to ignore the fixed stuffed columns in an AU-3 carrying a VC-3. When DISFS is set low, BIP-8 calculations include the fixed stuff columns in an STS-1 stream. This bit is ignored when the RPOP is processing an STS-3c (STM-1) stream. BLKBIP: When set high, the block BIP-8 bit (BLKBIP) indicates that path BIP-8 errors are to be accumulated on a block basis. A single BIP error is accumulated if any of the BIP-8 results indicates a mismatch. When BLKBIP is set low, BIP-8 errors are accumulated on a bit basis. ENSS: The enable size bit (ENSS) controls whether the SS bits in the payload pointer are used to determine offset changes in the pointer interpreter state machine. When a logic one is written to this bit, an incorrect SS bit pattern PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 132 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) (i.e.,10).will prevent RPOP from issuing NDF_enable, inc_ind, new_point and dec_ind indications. When a logic zero is written to this bit, the SS bits received do not affect active offset change events. SOS: The stuff opportunity spacing control bit (SOS) controls the spacing between consecutive pointer justification events on the receive stream. When a logic one is written to this bit, the definition of inc_ind and dec_ind indications includes the requirement that active offset changes have occurred a least three frame ago. When a logic zero is written to this bit, pointer justification indications in the receive stream are followed without regard to the proximity of previous active offset changes. Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 133 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x40: TPOP Control/Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type Function Unused Unused Unused Unused EXCFS Reserved DB3 PAIS Default 0 X X X 0 0 0 0 This register allows insertion of path level alarms and diagnostic signals. PAIS: The PAIS bit controls the insertion of STS path alarm indication signal. This register bit value is logically ORed with the input TPAIS. When a logic one is written to this bit position, the complete SPE, and the pointer bytes (H1, H2, and H3) are overwritten with the all-ones pattern. When a logic zero is written to this bit position, the pointer bytes and the SPE are processed normally. DB3: The DB3 bit controls the inversion of the B3 byte value. When a logic zero is written to this bit position, the B3 byte is transmitted uncorrupted. When a logic one is written to this bit position, the B3 byte is inverted which causes the insertion of eight path BIP-8 errors per frame. This bit overrides the state of the B3 error insertion mask controlled by the TPOHEN primary input. When a logic zero is written to this bit position, the B3 byte is transmitted uncorrupted. EXCFS: The fixed stuff column BIP-8 exclusion bit (EXCFS) controls the inclusion of bytes in the fixed stuff columns of the STS-1/AU-3 payload in path BIP-8 calculations. When EXCFS is a logic one, the value of the bytes in columns 30 and 59 do not affect the value of the path BIP-8 byte (B3). When EXCFS is logic zero, data in the fixed stuff bytes are included in the path BIP-8 calculations. This bit is only active if the TPOP is processing a STS-1 stream. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 134 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Reserved: The reserved bits must be programmed to logic zero for proper operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 135 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x41: TPOP Pointer Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused FTPTR SOS PLD NDF NSE PSE Reserved Default X 0 0 0 0 0 0 0 This register allows control over the transmitted payload pointer for diagnostic purposes. PSE: The PSE bit controls the insertion of positive pointer movements. A zero to one transition on this bit enables the insertion of a single positive pointer justification in the outgoing stream. This register bit is automatically cleared when the pointer movement is inserted. NSE: The NSE bit controls the insertion of negative pointer movements. A zero to one transition on this bit enables the insertion of a single negative pointer justification in the outgoing stream. This register bit is automatically cleared when the pointer movement is inserted. NDF: The NDF bit controls the insertion of new data flags in the inserted payload pointer. When a logic one is written to this bit position, the pattern contained in the NDF[3:0] bit positions in the TPOP Arbitrary Pointer MSB Register is inserted continuously in the payload pointer. When a logic zero is written to this bit position, the normal pattern (0110) is inserted in the payload pointer. PLD: The PLD bit controls the loading of the pointer value contained in the TPOP Arbitrary Pointer Registers. Normally the TPOP Arbitrary Pointer Registers PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 136 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) are written to set up the arbitrary new pointer value, the S-bit values, and the NDF pattern. A logic one is then written to this bit position to load the new pointer value. The new data flag bit positions are set to the programmed NDF pattern for the first frame; subsequent frames have the new data flag bit positions set to the normal pattern (0110) unless the NDF bit described above is set to a logic one. This bit is automatically cleared after the new payload pointer has been loaded. Note: When loading an out of range pointer (that is a pointer with a value greater than 782), the TPOP continues to operate with timing based on the last valid pointer value. The out of range pointer value will of course be inserted in the STS-12c/3c/1 stream. Although a valid SPE will continue to be generated, it is unlikely to be extracted by downstream circuitry which should be in a loss of pointer state. This bit is automatically cleared after the new payload pointer has been loaded. SOS: The SOS bit controls the stuff opportunity spacing between consecutive SPE positive or negative stuff events. When SOS is a logic zero, stuff events may be generated every frame as controlled by the PSE and NSE register bits described above. When SOS is a logic one, stuff events may be generated at a maximum rate of once every four frames. FTPTR: The force transmit pointer bit (FTPTR) enables the insertion of the pointer value contained in the Arbitrary Pointer Registers into the POUT[7:0] stream for diagnostic purposes. This allows upstream payload mapping circuitry to continue functioning normally and a valid SPE to continue to be generated, although it is unlikely to be extracted by downstream circuitry which should be in a loss of pointer state. If FTPTR is set to logic one, the APTR[9:0] bits of the Arbitrary Pointer Registers are inserted into the H1 and H2 bytes of the POUT[7:0] stream. At least one corrupted pointer is guaranteed to be sent. If FTPTR is a logic zero, a valid pointer is inserted. Reserved: The reserved bits must be programmed to logic zero for proper operation. For the J1 byte, the SPTB block can also be selected as a source when configured by a bit in the S/UNI-622 Master Configuration register. When a logic one is written to SRCJ1, the J1 byte is inserted from the data sampled on PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 137 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) primary input TPOH during the J1 byte position or from the SPTB block as controlled by the S/UNI-622 Master Configuration register. When a logic zero is written to SRCJ1, the J1 byte source is determined by input TPOHEN or the S/UNI-622 Master Configuration register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 138 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x43: TPOP Current Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTR[7:0]: The CPTR[7:0] bits, along with the CPTR[9:8] bits in the TPOP Current Pointer MSB Register reflect the value of the current payload pointer being inserted in the outgoing stream. The value may be changed by loading a new pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers, or by inserting positive and negative pointer movements using the PSE and NSE register bits. Type R R R R R R R R Function CPTR[7] CPTR[6] CPTR[5] CPTR[4] CPTR[3] CPTR[2] CPTR[1] CPTR[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 139 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x44: TPOP Current Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTR[9:8]: The CPTR[9:8] bits, along with the CPTR[7:0] bits in the TPOP Current Pointer LSB Register reflect the value of the current payload pointer being inserted in the outgoing stream. The value may be changed by loading a new pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers, or by inserting positive and negative pointer movements using the PSE and NSE register bits. It is recommended the CPTR[9:0] value be software debounced to ensure a correct value is received. R R Type Function Unused Unused Unused Unused Unused Unused CPTR[9] CPTR[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 140 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x45: TPOP Arbitrary Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function APTR[7] APTR[6] APTR[5] APTR[4] APTR[3] APTR[2] APTR[1] APTR[0] Default 0 0 0 0 0 0 0 0 This register allows an arbitrary pointer to be inserted for diagnostic purposes. APTR[7:0]: The APTR[7:0] bits, along with the APTR[9:8] bits in the TPOP Arbitrary Pointer MSB Register are used to set an arbitrary payload pointer value. The arbitrary pointer value is inserted in the outgoing stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register. If the FTPTR bit in the TPOP Pointer Control register is a logic one, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the POUT[7:0] stream. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 141 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x46: TPOP Arbitrary Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function NDF[3] NDF[2] NDF[1] NDF[0] S[1] S[0] APTR[9] APTR[8] Default 1 0 0 1 0 0 0 0 This register allows an arbitrary pointer to be inserted for diagnostic purposes. APTR[9:8]: The APTR[9:8] bits, along with the APTR[7:0] bits in the TPOP Arbitrary Pointer LSB Register are used to set an arbitrary payload pointer value. The arbitrary pointer value is inserted in the outgoing stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register. If the FTPTR bit in the TPOP Pointer Control register is a logic one, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the POUT[7:0] stream. S[1], S[0]: The S[1:0] bits contain the value inserted in the S[1:0] bit positions (also referred to as the unused bits) in the payload pointer. NDF[3:0]: The NDF[3:0] bits contain the value inserted in the NDF bit positions when an arbitrary new payload pointer value is inserted (using the PLD bit in the TPOP Pointer Control Register) or when new data flag generation is enabled using the NDF bit in the TPOP Pointer Control Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 142 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x47: TPOP Path Trace Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function J1[7] J1[6] J1[5] J1[4] J1[3] J1[2] J1[1] J1[0] Default 0 0 0 0 0 0 0 0 This register allows control over the path trace byte. J1[7:0]: The J1[7:0] bits are inserted in the J1 byte position in the POUT[7:0] stream when primary input TPOHEN is low during the path trace bit positions in the path overhead input stream, TPOH and when insertion via the SPTB is disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 143 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x48: TPOP Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function C2[7] C2[6] C2[5] C2[4] C2[3] C2[2] C2[1] C2[0] Default 0 0 0 1 0 0 1 1 This register allows control over the path signal label. Upon reset the register defaults to 13H, which represents "ATM Payload." C2[7:0]: The C2[7:0] bits are inserted in the C2 byte position in the POUT[7:0] stream when primary input TPOHEN is low during the path signal label bit positions in the path overhead input stream, TPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 144 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x49: TPOP Path Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function FEBE[3] FEBE[2] FEBE[1] FEBE[0] PRDI G1[2] G1[1] G1[0] Default 0 0 0 0 0 0 0 0 This register allows control over the path status byte. FEBE[3:0]: The FEBE[3:0] bits are inserted in the FEBE bit positions in the path status byte when the SRCG1 bit of the TPOP Source Control Register is logic zero and primary input TPOHEN is low during the path status FEBE bit positions in the path overhead input stream, TPOH. The value contained in FEBE[3:0] is cleared after being inserted in the path status byte. Any non-zero FEBE[3:0] value overwrites the value that would normally have been inserted based on the number of FEBEs accumulated on primary input FEBE during the last frame. When reading this register, a non-zero value in these bit positions indicates that the insertion of this value is still pending. PRDI: The PRDI bit controls the insertion of the path remote defect indication. This register bit value is logically ORed with the input TPRDI. When a logic one is written to this bit position, the PRDI bit position in the path status byte is set high. When a logic zero is written to this bit position, the PRDI bit position in the path status byte is set low. This bit has no effect if the SRCG1 bit of the TPOP Source Control Register is logic one or primary input TPOHEN is high during the path status remote defect indication bit position in the path overhead input stream, POH, in which case the value is inserted from TPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 145 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) G1[2], G1[1], G1[0]: The G1[2:0] bits are inserted in the unused bit positions in the path status byte when the SRCG1 bit of the TPOP Source Control Register is logic zero and primary input TPOHEN is low during the unused bit positions in the path overhead input stream, TPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 146 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x4A: TPOP Path User Channel Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function F2[7] F2[6] F2[5] F2[4] F2[3] F2[2] F2[1] F2[0] Default 0 0 0 0 0 0 0 0 This register allows control over the path user channel. F2[7:0]: The F2[7:0] bits are inserted in the F2 byte position in the POUT[7:0] stream when primary input TPOHEN is low during the path user channel bit positions in the path overhead input stream, TPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 147 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x4B: TPOP Path Growth #1 (Z3) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z3[7] Z3[6] Z3[5] Z3[4] Z3[3] Z3[2] Z3[1] Z3[0] Default 0 0 0 0 0 0 0 0 This register allows control over path growth byte #1 (Z3). Z3[7:0]: The Z3[7:0] bits are inserted in the Z3 byte position in the POUT[7:0] stream when primary input TPOHEN is low during the path growth #1 bit positions in the path overhead input stream, TPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 148 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x4C: TPOP Path Growth #2 (Z4) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z4[7] Z4[6] Z4[5] Z4[4] Z4[3] Z4[2] Z4[1] Z4[0] Default 0 0 0 0 0 0 0 0 This register allows control over path growth byte #2 (Z4). Z4[7:0]: The Z4[7:0] bits are inserted in the Z4 byte position in the POUT[7:0] stream when primary input TPOHEN is low during the path growth #2 bit positions in the path overhead input stream, TPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 149 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x4D TPOP Path Growth #3 (Z5) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z5[7] Z5[6] Z5[5] Z5[4] Z5[3] Z5[2] Z5[1] Z5[0] Default 0 0 0 0 0 0 0 0 This register allows control over path growth byte #3 (Z5). Z5[7:0]: The Z5[7:0] bits are inserted in the Z5 byte position in the POUT[7:0] stream when primary input TPOHEN is low during the path growth #3 bit positions in the path overhead input stream, TPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 150 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x50: RACP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST is set to logic zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST. DDSCR: The DDSCR bit controls the descrambling of the cell payload. When DDSCR is a logic one, cell payload descrambling is disabled. When DDSCR is a logic zero, payload descrambling is enabled. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to comparison. When HCSADD is a logic one, the polynomial is added, and the resulting HCS is compared. When HCSADD is a logic zero, the polynomial is not added, and the unmodified HCS is compared. Note that HCSADD can also be used to force the S/UNI-622 out of cell delineation. HCSPASS: The HCSPASS bit controls the dropping of cells based on the detection of an uncorrectable HCS error. When HCSPASS is a logic zero, cells containing an uncorrectable HCS error are dropped. When HCSPASS is a logic one, cells are passed to the receive FIFO regardless of errors detected in the HCS. In Type R/W R/W R/W R/W R/W R/W R/W R/W Function FSEN RXPTYP PASS DISCOR HCSPASS HCSADD DDSCR FIFORST Default 1 0 0 0 0 1 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 151 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) addition, the HCS verification finite state machine never exits the correction mode. Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states. DISCOR: The DISCOR bit disables the HCS error correction algorithm. When DISCOR is a logic zero, the error correction algorithm is enabled, and single bit errors detected in the cell header are corrected. When DISCOR is a logic one, the error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable HCS error. PASS: The PASS bit controls the function of the cell filter. When PASS is written with a logic zero, all cells which match the header cell filter and which have VPI and VCI fields set to 0 are dropped. When PASS is a logic one, the match header pattern registers are ignored and filtering of cells with VPI and VCI fields set to 0 is not performed. The default state of this bit together with the default states of the bits in the Match Mask and Match Pattern registers enable the dropping of cells containing all zero VCI and VPI fields. RXPTYP: The RXPTYP bit selects even or odd parity for outputs RXPRTY[1:0]. When RXPTYP is set to logic one, even parity is calculated for the output data on RDAT[15:0]; conversely, when RXPTYP is set to logic zero, odd parity is calculated for output data. In word parity mode, when RXPTYP is set to logic one, output RXPRTY[1] is the even parity bit for outputs RDAT[15:0]. In word parity mode, when RXPTYP is set to logic zero, output RXPRTY[1] is the odd parity bit for outputs RDAT[15:0]. (In word parity mode, RXPRTY[0] is held low.) In byte parity mode, when RXPTYP is set to logic one, output RXPRTY[1] is the even parity bit for outputs RDAT[15:8] and output RXPRTY[0] is the even parity bit for outputs RDAT[7:0]. In byte parity mode, when RXPTYP is set to logic zero, RXPRTY[1] is the odd parity bit for outputs RDAT[15:8] and output RXPRTY[0] is the odd parity bit for outputs RDAT[7:0]. FSEN: The active-high fix stuff control enable bit FSEN determines the payload mapping of ATM cells when STS-1 (AU-3) mapping is selected. When FSEN is set to logic one, the S/UNI-622 does not insert ATM cells into the two stuff columns in the SPE. When FSEN is set to logic zero, the S/UNI-622 inserts cells into the entire SPE. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 152 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x51: RACP Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FUDRI: The FUDRI bit is set high when a FIFO underrun occurs. This bit is reset immediately after a read to this register. FOVRI: The FOVRI bit is set high when a FIFO overrun occurs. This bit is reset immediately after a read to this register. UHCSI: The UHCSI bit is set high when an uncorrectable HCS error is detected. This bit is reset immediately after a read to this register. CHCSI: The CHCSI bit is set high when a correctable HCS error is detected. This bit is reset immediately after a read to this register. LCDI: The LCDI bit is set high when the S/UNI-622 enters or exits the loss of cell delineation state. Loss of cell delineation is declared when out of cell delineation persists for 4 ms or more. Loss of cell delineation is removed when out of cell delineation is absent for 4 ms. This bit is reset immediately after a read to this register. Type R R R R R R R R Function OCDV LCDV OCDI LCDI CHCSI UHCSI FOVRI FUDRI Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 153 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) OCDI: The OCDI bit is set high when a change of cell delineation state has occurred. The OCDI bit is set high when the S/UNI-622's cell delineation state machine transitions from the PRESYNC state to the SYNC state and from the SYNC state to the HUNT state. The cell delineation state machine transitions from the SYNC state to the HUNT state immediately when either loss of signal (LOS), loss of frame (LOF), loss of pointer (LOP), line AIS or path AIS is declared or when seven consecutive cells with incorrect HCS's are detected. The cell delineation state machine remains in HUNT state as long as one of the above alarms is active or if a cells with a correct HCS can not be found. This bit is reset immediately after a read to this register. LCDV: The LCDV bit indicates if the RACP-622 is in the loss of cell delineation state. When LCDV is set high, the RACP-622 is in the loss of cell delineation state. If LCDV is low, the RACP-622 is not in the loss of cell delineation state. OCDV: The OCDV bit indicates the cell delineation state. When OCDV is set high, the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states, and is hunting for the cell boundaries in the synchronous payload envelope. When OCDV is set low, the cell delineation state machine is in the 'SYNC' state and cells are passed through the receive FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 154 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x52: RACP Interrupt Enable/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function OCDE LCDE HCSE FIFOE LCDDROP RCALEVEL0 HCSFTR[1] HCSFTR[0] Default 0 0 0 0 0 1 0 0 HCSFTR[1:0]: The HCS filter bits, HSCFTR[1:0] indicate the number of error free cells required while in detection mode before reverting back to correction mode. Please refer to Figure 12 for details. Table 6 - HCSFTR[1:0] Cell Acceptance Threshold 00 01 10 11 One ATM cell with correct HCS before resumption of cell correction. Two ATM cells with correct HCS before resumption of cell correction. Four ATM cells with correct HCS before resumption of cell correction. Eight ATM cells with correct HCS before resumption of cell correction. RCALEVEL0: The active-high RCA level 0 bit, RCALEVEL0 determines what output RCA indicates when it transitions low. When RCALEVEL0 is set to logic one, a high to low transition on output RCA indicates that the receive FIFO is empty. When RCALEVEL0 is set to logic zero, a high to low transition on output RCA PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 155 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) indicates that the receive FIFO is near empty and contains only four words. Please refer to figures 36 a) and 36 b) for more information on RCALEVEL0. LCDDROP: The LCD drop bit, LCDDROP enables the dropping of cells while the , S/UNI-622 is in the loss of delineation (LCD) state. The S/UNI-622 enters the LCD state after continuously being out of cell delineation for 4 ms. Once in the LCD state, the S/UNI-622 exits the LCD state only after continuously being in cell delineation for 4 ms. When LCDDROP is set to logic one, received cells are not written into the receive FIFO unless the S/UNI-622 is not in the LCD state. When LCDDROP is set to logic zero, cells are written to the receive FIFO when the S/UNI-622 is in cell delineation, regardless whether the S/UNI-622 is in the LCD state or not. FIFOE: The FIFOE bit enables the generation of an interrupt due to a FIFO overrun. When FIFOE is set to logic one, the interrupt is enabled. HCSE: The HCSE bit enables the generation of an interrupt due to the detection of a correctable or an uncorrectable HCS error. When HCSE is set to logic one, the interrupt is enabled. LCDE: The LCDE bit enables the generation of an interrupt when loss of cell delineation is asserted and removed. When LCDE is set to logic one, the interrupt is enabled. OCDE: The OCDE bit enables the generation of an interrupt due to a change of cell delineation state. When OCDE is set to logic one, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 156 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x53: RACP Match Header Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GFC[3:0]: The GFC[3:0] bits contain the pattern to match in the first, second, third and fourth bits of the first octet of the 53-octet cell, in conjunction with the RACP Match Header Mask Register. The PASS bit in the RACP Control Register must be set to logic zero to enable dropping of cells matching this pattern. Note that an all-zeros pattern must be present in the VPI and VCI fields of the idle or unassigned cell. PTI[2:0]: The PTI[2:0] bits contain the pattern to match in the fifth, sixth and seventh bits of the fourth octet of the 53-octet cell, in conjunction with the RACP Match Header Mask Register. The PASS bit in the RACP Control Register must be set to logic zero to enable dropping of cells matching this pattern. CLP: The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53-octet cell, in conjunction with the RACP Match Header Mask Register. The PASS bit in the RACP Control Register must be set to logic zero to enable dropping of cells matching this pattern. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 157 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x54: RACP Match Header Mask Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MGFC[3:0]: The MGFC[3:0] bits contain the mask pattern for the first, second, third and fourth bits of the first octet of the 53-octet cell. This mask is applied to the RACP Match Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MPTI3:0]: The MPTI[3:0] bits contain the mask pattern for the fifth, sixth and seventh bits of the fourth octet of the 53-octet cell. This mask is applied to the RACP Match Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MCLP: The CLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53-octet cell. This mask is applied to the RACP Match Header Pattern Register to select the bits included in the cell filter. A logic one in this bit position enables the MCLP bit in the pattern register to be compared. A logic zero causes the masking of the MCLP bit. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MGFC[3] MGFC[2] MGFC[1] MGFC[0] MPTI2] MPTI[1] MPTI[0] MCLP Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 158 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x55: RACP Correctable HCS Error Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function CHCS[7] CHCS[6] CHCS[5] CHCS[4] CHCS[3] CHCS[2] CHCS[1] CHCS[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 159 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x56: RACP Correctable HCS Error Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHCS[11:0]: The CHCS[11:0] bits indicate the number of correctable HCS error events that occurred during the last accumulation interval. The contents of these registers are valid 7 s after a transfer is triggered by a write to the receive cell count register space, the correctable HCS error count register space, or to the uncorrectable HCS error count register space. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused CHCS[11] CHCS[10] CHCS[9] CHCS[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 160 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x57: RACP Uncorrectable HCS Error Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function UHCS[7] UHCS[6] UHCS[5] UHCS[4] UHCS[3] UHCS[2] UHCS[1] UHCS[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 161 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x58: RACP Uncorrectable HCS Error Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UHCS[11:0]: The UHCS[11:0] bits indicate the number of uncorrectable HCS error events that occurred during the last accumulation interval. The contents of these registers are valid 7 s after a transfer is triggered by a write to the receive cell count register space, the correctable HCS error count register space, or to the uncorrectable HCS error count register space. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused UHCS[11] UHCS[10] UHCS[9] UHCS[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 162 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x59: RACP Receive Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[7] RCELL[6] RCELL[5] RCELL[4] RCELL[3] RCELL[2] RCELL[1] RCELL[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 163 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x5A: RACP Receive Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[15] RCELL[14] RCELL[13] RCELL[12] RCELL[11] RCELL[10] RCELL[9] RCELL[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 164 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x5B: RACP Receive Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCELL[20:0]: The RCELL[20:0] bits indicate the number of cells receive and written into the receive FIFO during the last accumulation interval. Cells received and filtered due to HCS errors or Idle/Unassigned cell matches are not counted. The counter should be polled every second to avoid saturating. The contents of these registers are valid 7 s after a transfer is triggered by a write to the receive cell count register space, the correctable HCS error count register space, or to the uncorrectable HCS error count register space. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R R Type Function Unused Unused Unused RCELL[20] RCELL[19] RCELL[18] RCELL[17] RCELL[16] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 165 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x5C: GFC Control/Misc. Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RGFCE[3:0]: The receive GFC enable bits, RGFCE[3:0], determine which generic flow control bits are presented on output RGFC. If the enable bit for a GFC bit is set, the RGFC output changes, in the appropriate bit location, to the value of the corresponding GFC bit in the current cell; otherwise, RGFC is low. The RGFCE[3:0] bits are the mask bits for the GFC[3:0] bits. GFC[3], the most significant GFC bit (the first bit in the cell) is the first bit output on RGFC. For example, when RGFCE[3] is set to logic one, the GFC[3] bit is output on RGFC in the first RGFC bit period (marked by the RCP output). When RGFCE[3] is set to logic zero, RGFC is held low in the first RGFC bit period. RXBYTEPRTY: The receive byte parity, RXBYTEPRTY, mode bit selects between byte and word parity mode for outputs RXPRTY[1:0]. When the RXBYTEPRTY bit is set to logic one, byte parity mode is selected, otherwise, word parity mode is selected. In byte parity mode, RXPRTY[1] is the (odd or even) parity bit for outputs RDAT[15:8], and RXPRTY[0] is the parity bit for outputs RDAT[7:0]. In word parity mode, RXPRTY[1] is the (odd or even) parity bit calculated for all 16 outputs RDAT[15:0], and RXPRTY[0] is held low. Word parity mode can only be selected when the BUS8 input is low (i.e., the 16-bit FIFO interface is selected). CDDIS: The cell delineation disable bit, CDDIS, is used to defeat the cell delineation function of the S/UNI-622. When the CDDIS bit is set to logic one, HCS R/W R/W R/W R/W Type R/W R/W Function CDDIS RXBYTEPRTY Unused Unused RGFCE[3] RGFCE[2] RGFCE[1] RGFCE[0] Default 0 0 X X 1 1 1 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 166 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) errors are ignored, which makes every byte appear like a valid cell boundary. Ignoring HCS errors causes the cell delineation state machine to lock onto an arbitrary cell boundary and to enter and remain in the SYNC state. Once in the SYNC state, the incoming data is written to the FIFO. The CDDIS bit can be used to cause the S/UNI-622 to transparently pass SPE data through the FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 167 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x60: TACP Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four-cell transmit FIFO. When FIFORST is set to logic zero, the transmit FIFO operates normally. When FIFORST is set to logic one, the transmit FIFO is immediately emptied and reset to allow normal operation. Null/unassigned cells are transmitted until a subsequent cell is written to the transmit FIFO. DSCR: The DSCR bit controls the scrambling of the cell payload. When DSCR is a logic one, cell payload scrambling is disabled. When DSCR is a logic zero, payload scrambling is enabled. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to insertion in the synchronous payload envelope. When HCSADD is a logic one, the polynomial is added, and the resulting HCS is inserted. When HCSADD is a logic zero, the polynomial is not added, and the unmodified HCS is inserted. HCSADD takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO. HCSADD takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the HCS octet has been read from the transmit FIFO. Type R/W R R R/W R/W R/W R/W R/W Function FIFOE TSOCI FOVRI DHCS HCSB HCSADD DSCR FIFORST Default 0 X X 0 0 1 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 168 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) HCSB: The HCSB bit enables the internal generation and insertion of the HCS octet into the transmit cell stream. When HCSB is a logic zero, the HCS is generated and inserted internally. When HCSB is a logic one, the HCS octet read from the FIFO is inserted transparently into the transmit cell stream. An HCS is generated for null/unassigned cells regardless of the state of this bit. An HCS is generated for null/unassigned cells regardless of the state of this bit. DHCS: The DHCS bit controls the insertion of HCS errors for diagnostic purposes. When DHCS is set to logic one, the HCS octet is inverted prior to insertion in the synchronous payload envelope. DHCS takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO. FOVRI: The FOVRI bit is set high when a FIFO overrun occurs. This bit is reset immediately after a read to this register TSOCI: The TSOCI bit is set high when the TSOC input is sampled high during any position other than the first word of the cell data structure. The write address counter is reset to the first word of the data structure when TSOC is sampled high. This bit is reset immediately after a read to this register. FIFOE: The FIFOE bit enables the generation of an interrupt due to a FIFO overrun error condition or when the TSOC input is sampled high during any position other than the first word of the cell data structure. When FIFOE is set to logic one, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 169 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x61: TACP Idle/Unassigned Cell Header Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GFC[3:0]: The GFC[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. Cell rate decoupling is accomplished by transmitting idle/unassigned cells when the TACP detects that no outstanding cells exist in the transmit FIFO. The all zeros pattern is transmitted in the VCI and VPI fields of the idle cell. PTI[3:0]: The PTI[3:0] bits contain the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted when the TACP detects that no outstanding cells exist in the transmit FIFO. CLP: The CLP bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted when the TACP detects that no outstanding cells exist in the transmit FIFO. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 170 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x62: TACP Idle/Unassigned Cell Payload Octet Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICP[7:0]: The ICP[7:0] bits contain the pattern inserted in the payload octets of the idle or unassigned cell. Cell rate decoupling is accomplished by transmitting idle/unassigned cells when the TACP detects that no outstanding cells exist in the transmit FIFO. Bit ICP[7] corresponds to the most significant bit of the octet, the first bit transmitted. Type R/W R/W R/W R/W R/W R/W R/W R/W Function ICP[7] ICP[6] ICP[5] ICP[4] ICP[3] ICP[2] ICP[1] ICP[0] Default 0 1 1 0 1 0 1 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 171 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x63: TACP FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCSCTLEB: The active-low HCS control enable, HCSCTLEB bit enables the XORing of the HCS Control byte with the generated HCS before insertion into the SPE stream. When set to logic zero, the HCS Control byte provided in the third word of the 27-word data structure is XORed with the generated HCS. When set to logic one, XORing is disabled and the HCS Control byte is ignored. TCALEVEL0: The active-high TCA level 0 bit, TCALEVEL0 determines what output TCA indicates when it transitions low. When TCALEVEL0 is set to logic one, output TCA indicates that the transmit FIFO is full and can accept no more writes. When TCALEVEL0 is set to logic zero, output TCA indicates that the transmit FIFO is near full and can accept no more than four additional writes. Please refer to figure 38 for more information on TCALEVEL0. FIFODP[1:0]: The FIFODP[1:0] bits determine the transmit FIFO cell depth. FIFO depth control may be important in systems where the cell latency through the transmit FIFO must be minimized. When the FIFO is filled to the specified depth, the transmit cell available signal (TCA) transitions to a logic zero. The selectable FIFO cell depths are shown below. Use of 1 or 2 cell FIFO DEPTHs is not recommended because a link utilisation of 100% can not be guaranteed. Type R/W R/W R R R/W R/W R/W R/W Function TXPTYP TXPRTYE TXPRTYI[1] TXPRTYI[0] FIFODP[1] FIFODP[0] TCALEVEL0 HCSCTLEB Default 0 0 X X 0 0 0 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 172 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Table 7 FIFODP[1] 0 0 1 1 FIFODP[0] 0 1 0 1 FIFO DEPTH 4 cells 3 cells 2 cells 1 cell TXPRTYI[1:0]: The TXPRTYI[1:0] bits indicate if a parity error was detected on the TDAT[15:0] bus. When logic one, the TXPRTYI[1] bit indicates a parity error over inputs TDAT[15:0] (in word parity mode) or TDAT[15:8] (in byte parity mode). Similarly, when logic one, the TXPRTYI[0] bit indicates a parity error over inputs TDAT[7:0] in byte parity mode. (TXPRTYI[0] is unused in word parity mode, i.e., when the TXBYTEPRTY register bit is logic zero). Both parity error indication bits are cleared when this register is read. Odd or even parity is selected using the TXPTYP bit. TXPRTYE: The TXPRTYE bit enables transmit parity interrupts. When set to logic one, parity errors on inputs TDAT[15:0] are indicated using bits TXPRTYI[1:0] and output INTB. When set to logic zero, parity errors are indicated using bits TXPRTYI[1:0] but are not indicated on output INTB. TXPTYP: The TXPTYP bit selects even or odd parity for inputs TXPRTY[1:0]. In byte parity mode, when TXPTYP is set to logic one, input TXPRTY[1] is the even parity bit for inputs TDAT[15:8] while input TXPRTY[0] is the even parity bit for inputs TDAT[7:0]. In byte parity mode, when set to logic zero, inputs TXPRTY[1:0] are the odd parity bits for inputs TDAT[15:0]. In word parity mode, when TXPTYP is set to logic one, input TXPRTY[1] is the even parity bit for inputs TDAT[15:0] and TXPRTY[0] is ignored. In word parity mode, when TXPTYP is set to logic zero, input TXPRTY[1] is the odd parity bit for inputs TDAT[15:0] and TXPRTY[0] is ignored. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 173 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x64: TACP Transmit Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[7] TCELL[6] TCELL[5] TCELL[4] TCELL[3] TCELL[2] TCELL[1] TCELL[0] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 174 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x65: TACP Transmit Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[15] TCELL[14] TCELL[13] TCELL[12] TCELL[11] TCELL[10] TCELL[9] TCELL[8] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 175 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x66: TACP Transmit Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCELL[20:0]: The TCELL[20:0] bits indicate the number of cells read from the transmit FIFO and inserted into the SPE during the last accumulation interval. Idle/Unassigned cells inserted into the SPE are not counted. The counter should be polled every second to avoid saturating. The contents of these registers are valid 7 s after a transfer is triggered by a write to the transmit cell count register space. The count can also be polled by writing to the S/UNI-622 Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R R Type Function Unused Unused Unused TCELL[20] TCELL[19] TCELL[18] TCELL[17] TCELL[16] Default X X X X X X X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 176 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x67: TACP Fixed Stuff / GFC Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TGFCE[3] TGFCE[2] TGFCE[1] TGFCE[0] FSEN TXBYTEPRTY FIXBYTE[1] FIXBYTE[0] Default 0 0 0 0 1 0 0 0 FIXBYTE[1:0]: The FIXBYTE[1:0] bits identify the byte pattern inserted into fixed byte columns of the synchronous payload envelope. Table 8 FIXBYTE[1] 0 0 1 1 TXBYTEPRTY: The active-high transmit byte parity selector bit, TXBYTEPRTY, selects between byte parity (2 parity bits, each over an 8-bit byte) or word parity (1 parity bit over a 16-bit word). If TXBYTEPRTY is set high, TXPRTY[1] is expected to be the parity over TDAT[15:8] and TXPRTY[0] is expected to be the parity over TDAT[7:0]. If TXBYTEPRTY is set low, TXPRTY[1] is expected to be the parity over TDAT[15:0] and TXPRTY[0] is ignored. FSEN: The active-high fix stuff control enable bit, FSEN determines the payload mapping of ATM cells when STS-1 (AU-3) mapping is selected. When FSEN FIXBYTE[0] 0 1 0 1 BYTE 00H 55H AAH FFH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 177 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) is set to logic one, the S/UNI-622 does not map ATM cells into columns 30 and 59 of a STS-1 SPE. When FSEN is set to logic zero, the S/UNI-622 maps ATM cells into the entire STS-1 SPE. The FSEN bit is ignored in STS-12c (STM-4c) and STS-3c (STM-1) modes. TGFCE[3:0]: The TGFCE[3:0] bits select the source of the GFC bits. For example, when the TGFCE[3] bit is set high, the TGFC input is used to source the GFC[3] bit of transmit cell headers. If the TGFCE[3] bit is set low, the GFC[3] bit of an idle/unassigned cell is programmed in the TACP Idle/Unassigned Cell Header register while the GFC[3] bit of a user cell read from the FIFO is transmitted unaltered. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 178 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x68 SPTB Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused RRAMACC RTIUIE RTIMIE PER5 TNULL NOSYNC LEN16 Default X 0 0 0 0 1 0 0 This register controls the receive and transmit portions of the SPTB. LEN16: The path trace message length bit (LEN16) selects the length of the path trace message to be 16 bytes or 64 bytes. When set high, a 16-byte path trace message is selected. If set low, a 64-byte path trace message is selected. NOSYNC: The path trace message synchronization disable bit (NOSYNC) disables the writing of the path trace message into the trace buffer to be synchronized to the content of the message. When LEN16 is set high and NOSYNC is set low, the receive path trace message byte with its most significant bit set will be written to the first location in the buffer. When LEN16 is set low, and NOSYNC is also set low, the byte after the carriage return/linefeed (CR/LF) sequence will be written to the first location in the buffer. When NOSYNC is set high, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. TNULL: The transmit null bit (TNULL) controls the insertion of an all-zero path trace identifier message in the transmit stream. When TNULL is set high, the contents of the transmit buffer is ignored and all-zeros bytes are provided to the TPOP block. When TNULL is set low the contents of the transmit path trace buffer is sent to TPOP for insertion into the J1 transmit path overhead PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 179 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) byte. TNULL should be set high before changing the contents of the trace buffer to avoid sending partial messages. PER5: The receive trace identifier persistence bit (PER5) control the number of times a path trace identifier message must be received unchanged before being accepted. When PER5 is set high, a message is accepted when it is received unchanged five times consecutively. When PER5 is set low, the message is accepted after three identical repetitions. RTIMIE: The receive path trace identifier message mismatch interrupt enable bit (RTIMIE) controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state from match to mismatch and vice versa. When RTIMIE is set high, changes in match state activates the interrupt (INTB) output. When RTIMIE is set low, path trace identifier message state changes will not affect INTB. RTIUIE: The receive path trace identifier message unstable interrupt enable bit (RTIUIE) controls the activation of the interrupt output when the receive identifier message state changes from stable to unstable and vice versa. The unstable state is entered when the current identifier message differs from the previous message for six consecutive messages. The stable state is entered when the same identifier message is received for three or five consecutive messages as controlled by the PER5 bit. When RTIUIE is set high, changes in the received path trace identifier message stable/unstable state of will activate the interrupt (INTB) output. When RTIUIE is set low, path trace identifier state changes will not affect INTB. RRAMACC: The receive RAM access control bit (RRAMACC) directs read and writes access to between the receive and transmit portion of the S/UNI-622. When RRAMACC is set high, subsequent microprocessor read and write accesses are directed to the receive side trace buffers. When RRAMACC is set low, microprocessor accesses are directed to the transmit side trace buffer. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 180 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x69: SPTB Path Trace Identifier Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R Function BUSY Unused Unused Unused RTIUI RTIUV RTIMI RTIMV Default 0 X X X X X X X This register reports the path trace identifier status of the SPTB. RTIMV: The receive path trace identifier message mismatch status bit (RTIMV) reports the match/mismatch status of the identifier message framer. RTIMV is set high when the accepted identifier message differs from the expected message written by the microprocessor. RTIMV is set low when the accepted message matches the expected message. RTIMI: The receive path trace identifier mismatch interrupt status bit (RTIMI) is set high when match/mismatch status of the trace identifier framer changes state. This bit and the interrupt are cleared when this register is read. RTIUV: The receive path trace identifier message unstable status bit (RTIUV) reports the stable/unstable status of the identifier message framer. RTIUV is set high when the current received path trace identifier message has not matched the previous message for eight consecutive messages. RTIUV is set low when the current message becomes the accepted message as determined by the PER5 bit in the SPTB Control register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 181 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) RTIUI: The receive path trace identifier message unstable interrupt status bit (RTIUI) is set high when stable/unstable status of the trace identifier framer changes state. This bit and the interrupt are cleared when this register is read. BUSY: The BUSY bit reports whether a previously initiated indirect read or write to a message buffer has been completed. BUSY is set high upon writing to the SPTB Indirect Address register, and stays high until the initiated access has completed. At which point, BUSY is set low. This register should be polled to determine when new data is available in the SPTB Indirect Data register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 182 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x6A: SPTB Indirect Address Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0] Default 0 0 0 0 0 0 0 0 This register supplies the address used to index into path trace identifier buffers. A[6:0]: The indirect read address bits (A[6:0]) indexes into the path trace identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference the receive capture page while addresses 64 to 127 reference the receive expected page. The receive capture page contains the identifier bytes extracted from the receive stream. The receive expected page contains the expected trace identifier message down-loaded from the microprocessor. When RRAMACC is set low, addresses 0 to 63 reference the transmit message buffer which contains the identifier message to be inserted in the J1 bytes of the transmit stream. For this case, addresses 64 to 127 are unused and must not be accessed. RWB: The access control bit (RWB) selects between an indirect read or write access to the static page of the path trace message buffer. Writing to this register initiates an external microprocessor access to the static page of the path trace message buffer. When RWB is set high, a read access is initiated. The data read can be found in the SPTB Indirect Data register. When RWB is set low, a write access is initiated. The data in the SPTB Indirect Data register will be written to the addressed location in the static page. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 183 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x6B: SPTB Indirect Data Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default 0 0 0 0 0 0 0 0 This register contains the data read from the path trace message buffer after a read operation or the data to be written into the buffer before a write operation. D[7:0]: The indirect data bits (D[7:0]) reports the data read from a message buffer after an indirect read operation has completed. The data to be written to a buffer must be set up in this register before initiating an indirect write operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 184 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x6C: SPTB Expected Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EPSL7 EPSL6 EPSL5 EPSL4 EPSL3 EPSL2 EPSL1 EPSL0 Default 0 0 0 0 0 0 0 0 This register contains the expected path signal label byte in the receive stream.. EPSL[7:0]: The EPSL7 - EPSL0 bits contain the expected path signal label byte (C2). EPSL[7:0] is compared with the accepted path signal label extracted from the receive stream. A path signal label mismatch (PSLM) is declared if the accepted PSL differs from the expected PSL. If enabled, an interrupt is asserted upon declaration and removal of PSLM. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 185 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x6D: SPTB Path Signal Label Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R/W R/W Function RPSLUIE RPSLMIE Unused Unused RPSLUI RPSLUV RPSLMI RPSLMV Default 0 0 X X X X X X This register reports the path signal label status of the SPTB. RPSLMV: The receive path signal label mismatch status bit (RPSLMV) reports the match/mismatch status between the expected and the accepted path signal label. RPSLMV is set high when the accepted PSL differs from the expected PSL written by the microprocessor. PSLMV is set low when the accepted PSL matches the expected PSL. RPSLMI: The receive path signal label mismatch interrupt status bit (RPSLMI) is set high when the match/mismatch status between the accepted and the expected path signal label changes state. This bit (and the interrupt) are cleared when this register is read. RPSLUV: The receive path signal label unstable status bit (RPSLUV) reports the stable/unstable status of the path signal label in the receive stream. RPSLUV is set high when the current received C2 byte differs from the previous C2 byte for five consecutive frames. RPSLUV is set low when the same PSL code is received for five consecutive frames. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 186 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) RPSLUI: The receive path signal label unstable interrupt status bit (RPSLUI) is set high when the stable/unstable status of the path signal label changes state. This bit and the interrupt are cleared when this register is read. RPSLMIE: The receive path signal label mismatch interrupt enable bit (RPSLMIE) controls the activation of the interrupt output when the comparison between accepted and the expected path signal label changes state from match to mismatch and vice versa. When RPSLMIE is set high, changes in match state activates the interrupt (INTB) output. When RPSLMIE is set low, path signal label state changes will not affect INTB. RPSLUIE: The receive path signal label unstable interrupt enable bit (RPSLUIE) controls the activation of the interrupt output when the received path signal label changes state from stable to unstable and vice versa. When RPSLUIE is set high, changes in stable state activates the interrupt (INTB) output. When RPSLUIE is set low, path signal label state changes will not affect INTB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 187 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x70: BERM Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Type R/W Function BERTEN Unused Unused Unused Unused Unused Unused BERIE Default 0 X X X X X X 0 This register controls the automatic bit error rate alarm circuitry. BERIE: The Bit Error Rate interrupt enable bit enables and disables BERI interrupts. When BERIE is set high, BERI interrupts are reflected on output INTB. When BERIE is set low, BERI interrupts are not reflected on output INTB. BERTEN: The Bit Error Rate test enable bit enables and disables automatic monitoring of line BIP errors. When BERTEN is set high, the S/UNI-622 continuously accumulates line BIP errors over a period defined in the BERM Line BIP Accumulation Period registers. If, at any point, the accumulated count equals the value defined in the BERM Line BIP Threshold registers, an interrupt is asserted. Both the BERM Line BIP Accumulation Period and BERM Line BIP Threshold registers should be set up before the BERTEN bit is set high. When BERTEN is set low, the BIP accumulation logic is disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 188 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x71: BERM Interrupt Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Type W W W W Function BERM_TST[3] BERM_TST[2] BERM_TST[1] BERM_TST[0] Unused Unused Unused BERI Default 0 0 0 0 X X X X This register indicates the automatic bit error rate interrupts. BERIE: The Bit Error Rate interrupt bit indicates that the incoming bit error rate has exceeded the user programmed maximum. When BERI is set high, the S/UNI-622 has accumulated more line BIP errors then the number indicated in the Line BIP Threshold registers over the period defined by the BIP Accumulation Period registers. BERI is cleared when this register is read. BERM_TST[3:0]: The BERM_TST[3:0] bits are used for production test of the BERM block. The BERM_TST[3] bit is the LB_AP_REGLOAD / LB_AP_REG_COMPARE bit. The BERM_TST[2] bit is the LB_AP_REGHOLD bit. The BERM_TST[1] bit is the LB_TH_REGLOAD / LB_TH_REG_COMPARE bit. The BERM_TST[0] bit is the LB_TH_REGHOLD bit. Please see the Test Vector Description section for details. These bits are write-only bits. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 189 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x72: BERM Line BIP Accumulation Period LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_AP[7] LB_AP[6] LB_AP[5] LB_AP[4] LB_AP[3] LB_AP[2] LB_AP[1] LB_AP[0] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 190 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x73: BERM Line BIP Accumulation Period MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LB_AP[15:0]: The LB_AP[15:0] bits represent the number of 125 s frames which define a line BIP accumulation period. Please refer to the Operations section for recommended values of LB_AP[15:0] to detect various bit error rates. Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_AP[15] LB_AP[14] LB_AP[13] LB_AP[12] LB_AP[11] LB_AP[10] LB_AP[9] LB_AP[8] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 191 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x74: BERM Line BIP Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_TH[7] LB_TH[6] LB_TH[5] LB_TH[4] LB_TH[3] LB_TH[2] LB_TH[1] LB_TH[0] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 192 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x75: BERM Line BIP Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LB_TH[15:0]: The LB_TH[15:0] bits represent the allowable number of line BIP errors that can be accumulated during a line BIP accumulation period before an BERI interrupt is asserted. Please refer to the Operations section for recommended values of LB_TH[15:0] to detect various bit error rates. Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_TH[15] LB_TH[14] LB_TH[13] LB_TH[12] LB_TH[11] LB_TH[10] LB_TH[9] LB_TH[8] Default 0 0 0 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 193 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 11 TEST FEATURES DESCRIPTION Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the S/UNI-622. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[7]) is high. Test mode registers may also be used for board testing. When all of the TSBs within the S/UNI-622 are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "Test Mode 0" for details). In addition, the S/UNI-622 also supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port for use in board testing. All digital device inputs may be read and all digital device outputs may be forced with the exception of the POUT[7:0] bus via the JTAG test port. 11.1 Test Mode Register Memory Map Table 9 Address 0x00-0x7F 0x80 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E-0x8F 0x90 0x91 Register Normal Mode Registers Master Test PISO Test Register 0 PISO Test Register 1 PISO Test Register 2 Reserved SIPO Test Register 0 SIPO Test Register 1 Reserved RSOP Test Register 0 RSOP Test Register 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 194 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Address 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B-0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC-0xAF 0xB0 0xB1 0xB2 0xB3-0xBF 0xC0 Register RSOP Test Register 2 RSOP Test Register 3 TSOP Test Register 0 TSOP Test Register 1 TSOP Test Register 2 TSOP Test Register 3 RLOP Test Register 0 RLOP Test Register 1 RLOP Test Register 2 Reserved TLOP Test Register 0 TLOP Test Register 1 TLOP Test Register 2 TLOP Test Register 3 BIDX Test Register 0 BIDX Test Register 1 BIMX Test Register 0 BIMX Test Register 1 SSTB Test Register 0 SSTB Test Register 1 SSTB Test Register 2 SSTB Test Register 3 Reserved RPOP Test Register 0 RPOP Test Register 1 RPOP Test Register 2 Reserved TPOP Test Register 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 195 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Address 0xC1 0xC2 0xC3 0xC4 0xC5-0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5-0xDF 0xE0 0xE1 0xE2 0xE3 0xE4-0xE7 0xE8 0xE9 0xEA 0xEB 0xEC-0xFF Register TPOP Test Register 1 TPOP Test Register 2 TPOP Test Register 3 TPOP Test Register 4 Reserved RACP Test Register 0 RACP Test Register 1 RACP Test Register 2 RACP Test Register 3 RACP Test Register 4 Reserved TACP Test Register 0 TACP Test Register 1 TACP Test Register 2 TACP Test Register 3 Reserved SPTB Test Register 0 SPTB Test Register 1 SPTB Test Register 2 SPTB Test Register 3 Reserved Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 196 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 2. Writable test mode register bits are not initialized upon reset unless otherwise noted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 197 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Register 0x80: Master Test Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W W R/W W R/W Type W Function DS27_53 Unused Unused PMCTST DBCTRL IOTST HIZDATA HIZIO Default 1 X X X X 0 X 0 This register is used to enable S/UNI-622 test features. All bits, except PMCTST, are reset to zero by a reset of the S/UNI-622. HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-622 . While the HIZIO bit is a logic one, all output pins of the S/UNI-622 except the data bus and output TDO are held tri-state. The microprocessor interface is still active. While the HIZDATA bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL bit. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each TSB block in the S/UNI-622 for board level testing. When IOTST is a logic one, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequentially the device outputs (refer to the "Test Mode 0 Details" in the "Test Features" section). DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST are logic one, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-622 to drive the data bus and holding the CSB pin low tri-states the data bus. The PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 198 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. PMCTST: The PMCTST bit is used to configure the S/UNI-622 for PMC's manufacturing tests. When PMCTST is set to logic one, the S/UNI-622 microprocessor port becomes the test access port used to run the PMC "canned" manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. DS27_53: The DS27_53 bit is use to select between the long data structure (27 words in 16-bit mode and 53 bytes in 8-bit mode) and the short data structure (26 words in 16-bit mode and 52 bytes in 8-bit mode). When DS27_53 is set to logic one, the RACP-622 and TACP-622 blocks are configured to operate with the long data structure; when DS27_53 is set to logic zerio, the RACP-622 and TACP-622 blocks are configured to operate with the short data structure. 11.2 Test Mode 0 Details In test mode 0, the S/UNI-622 allows the logic levels on the device inputs to be read through the microprocessor interface and allows the device outputs to be forced to either logic level through the microprocessor interface. The IOTST bit in the Master Test register must be set to logic one to access the device I/O. To enable test mode 0, the IOTST bit in the Master Test register is set to logic one and the following addresses must be written with 00H: 89H, 8DH, 91H, 95H, 99H, A1H, A5H, A7H, A9H, B1H, C1H, D1H, E1H, E9H. Clock edges must be provided on inputs TCLK and PICLK when these clocks are not being tested. Reading the following address locations returns the values on the indicated inputs: Table 10 Addr 08H 0FH 8BH 8CH 90H 92H PIN[7] PIN[6] PIN[5] PIN[4] PIN[3] PIN[2] TTOH[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PIP[3] TTOH[3] Bit 2 PIP[2] TTOH[2] Bit 1 PIP[1] TTOH[1] TSICLK1 RSICLK2 FPIN4 PIN[1] RSIN3 PICLK PIN[0] Bit 0 PIP[0] TTOHEN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 199 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Addr 94H A0H C0H C3H C4H E0H Bit 7 TSUC5 Bit 6 TSOW5 TLOW Bit 5 TSD TLD Bit 4 Bit 3 Bit 2 TLAIS Bit 1 Bit 0 TLDRI6 TPRDI7 TPAIS TPOH8 TCLK TPOHEN9 TFP XOFF TGFC The following inputs cannot be read using the IOTST feature: TDAT[15:0], TSOC, TXPRTY[1:0], TWRENB, TFCLK, FPOS, RFCLK, TSEN, RRDENB, D[7:0], A[7:0], ALE, CSB, WRB, RDB, RSTB, TRSTB, TMS, TCK, and TDI. 1. To read TSICLK, TMODE[1:0] should be set to binary '10' in the Master Configuration Register and LOOPT should be set to 0 in the Master Control/Monitor Register. 2. To read RSICLK, RMODE[1:0] should be set to binary '10' in the Master Configuration Register and DLE should be set to 0 in the Master Control/Monitor Register. 3. To read RSIN, RMODE[1:0] should be set to binary '10' in the Master Configuration Register and DLE should be set to 0 in the Master Control/Monitor Register. Additionally, RSICLK must be toggled to a logic zero and then back to a logic one to capture the value on the RSIN input. 4. To read FPIN, FPOS must be set to a logic zero. 5. TOWCLK must be toggled to a logic zero and then back to a logic one in order to capture the value on these inputs. 6. To read TLDRI, AUTOLRDI must be set to 0 in the Master Auto Alarm Register. 7. To read TPRDI, AUTOPRDI must be set to 0 in the Master Auto Alarm Register. 8. To read TPOH, TPOHEN must be set to a logic one. 9. To read TPOHEN, TPTBEN must be set to 0 in the Master Configuration Register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 200 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Writing the following address locations forces the outputs to the value in the corresponding bit position (zeros should be written to all unused test register locations): Table 11 Addr 06H 8BH 8CH 90H 92H 94H 96H POUT[7] POUT[6] POUT[5] POUT[4] LOF RSOW OOF LOS RSD TSDCLK POUT[3] POUT[2] POUT[1] POUT[0]/ FPOUT 98H 9AH 9BH A0H A6H B0H B2H B3H C3H D0H E0H RCP LOP PRDI TPOHCLK RGFC RPOHFP TPOHFP LCD TCP RPOH RPOHCLK TTOHCLK RTOHFP3 RTOHCLK3 TOWCLK TTOHFP PAIS LRDI LAIS RLD RTOH[4]3 TLDCLK GTOCLK4 OHFP3 RLDCLK RTOH[3]3 RLOW RTOH[2]3 ROWCLK RTOH[1]3 RSDCLK RSUC Bit 7 Bit 6 Bit 5 POP[5] Bit 4 POP[4] Bit 3 POP[3] INT1 Bit 2 POP[2] Bit 1 POP[1] TSOUT2 GROCLK3 Bit 0 POP[0] The following outputs can not be controlled using the IOTST feature: TCA, RSOC, RDAT[15:0], RXPRTY[1:0], RCA, D[7:0], and TDO. 1. INT corresponds to output INTB. INTB is an open drain output and should be pulled high for proper operation. Writing a logic one to the INT bit allows the S/UNI-622 to drive INTB low. Writing a logic zero to the INT bit tristates the INTB output. 2. After the TSOUT value has been written to the test bit, TSICLK must be toggled to a logic low and then back to a logic high before the test value appears on the TSOUT output pin. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 201 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 3. To control these outputs, RMODE[1:0] should be set to binary '10' in the Master Configuration Register. 4. To control GTOCLK, TMODE[1:0] should be set to binary '11' in the Master Configuration Register. 11.3 JTAG Test Port The S/UNI-622 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP device input logic levels can be read, device outputs can be , forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Table 12 - Instruction Register Length - 3 bits Instructions Register EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Identification Register Length - 32 bits Version number - 0H Part Number - 5355H Manufacturer's identification code - 0CDH Selected Codes, IR[2:0] Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass 000 001 010 011 100 101 110 111 Instruction PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 202 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Device identification - 053550CDH Boundary Scan Register The boundary scan register is made up of 155 boundary scan cells, divided into input observation (in_cell), output (out_cell), and bidirectional (io_cell) cells. These cells are detailed in the pages which follow. The first 32 cells form the ID code register, and carry the code 053550CD. The cells are arranged as follows: Pin/ Enable Register Bit Cell Type I.D. Bit Pin/ Enable Register Bit Cell Type I.D. Bit NOTES: 1. OENB is the active low output enable for D[7:0]. 2. RDATENB is the active low output enable for RSOC, RDAT[15:0], and RXPRTY[1:0]. 3. When set high, INTB will be set to high impedance. 4. HIZ is the active low output enable for all OUT_CELL types except D[7:0], RXPRTY[1:0], RDAT[15:0], and INTB 5. A[7] is the first bit of the boundary scan chain. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 203 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 13 IDCODE - Input Observation Cell (IN_CELL) Scan Chain Out Input Pad G1 G2 SHIFT-DR INPUT to internal logic I.D. Code bit CLOCK-DR 12 1 2 MUX 12 12 Scan Chain In D C In this diagram and those that follow, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the table above. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 204 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 14 - Output Cell (OUT_CELL) S can Chain Out EXT EST OUT PUT or Enable from s ys t em logic IDCODE S HI F T - DR G 1 1 G 1 G 2 1 1 1 1 2 2 MUX 2 2 1 OUT PUT or Enable MUX D C D C I.D. code bit CL OCK -DR UPDAT E- DR S can Chain In Figure 15 - Bidirectional Cell (IO_CELL) Scan Chain Out INPUT to internal logic EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin G1 1 G1 G2 12 1 2 MUX 12 12 1 MUX OUTPUT to pin D C D C I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 205 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 16 - Layout of Output Enable and Bidirectional Cells Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) OUT_CELL Scan Chain In Scan Chain Out INPUT to internal logic OUTPUT from internal logic IO_CELL I/O PAD Scan Chain In PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 206 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 12 OPERATION ATM Mapping and Overhead Byte Usage The S/UNI-622 processes the ATM cell mappings for STS-12c (STS-4c), STS-3c (STM-1) and STS-1 as shown below in Figures 10 through 12. The S/UNI-622 processes the subset of the complete transport and path overhead required to support ATM UNIs and NNIs. In addition, the S/UNI-622 provides support for the APS bytes, the data communication channels and provides full external control and observability of the transport and path overhead bytes. Figure 17 shows the STS-1 mapping. The S/UNI-622 supports two STS-1 mappings, one with the indicated stuff columns containing fixed stuff bytes and the other with the indicated stuff columns used for ATM cells. Figure 17 - STS-1 Mapping 90 bytes 3 bytes STS-1 Transport Overhead A1 A2 C1 87 bytes Column 1 P A T H O V E R H E A D Column 30 ATM Cell Column 59 Section Overhead Pointer B1 H1 H2 H3 B2 K2 F I X E D ATM Cell S T U F F F I X E D S T U F F ATM Cell 9 bytes Line Overhead Z2 * Fixed stuff columns optionally filled with cells Figure 18 shows the STS-3c (STM-1) mapping. In this mapping, no stuff columns are included in the SPE. The entire SPE is used for ATM cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 207 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 18 - STS-3c (STM-1) Mapping 270 bytes 9 bytes STS-3c Transport Overhead 261 bytes Section Overhead Pointer P A T H O V E R H E A D ATM Cell Line Overhead ATM Cell 9 bytes ATM Cell ATM Cell STS-3c Transport Overhead A1 A1 A1 A2 A2 A2 C1 C1 C1 B1 H1 H1 H1 H2 H2 H2 H3 H3 H3 B2 B2 B2 K2 Z2 Figure 19 shows the STS-12c (STM-4c) mapping. For this mapping, three stuff columns are provided. In this mode of operation, the S/UNI-622 always stuffs the fixed stuff columns with the byte contained in the TACP Fixed Stuff / GFC register. No other options are provided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 208 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 19 - STS-12c (STM-4c) ATM Mapping 1080 bytes 36 bytes STS-12c Transport Overhead 1044 bytes Path Overhead J1 Section Overhead Pointer B3 C2 G1 F I X E D S T U F F F I X E D S T U F F F I X E D S T U F F ATM Cell Line Overhead ATM Cell 9 bytes ATM Cell STS-12c Transport Overhead A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 B1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H1 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H2 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 H3 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 K2 Z2 Transport Overhead Bytes A1, A2: The frame alignment bytes (A1, A2) locate the SONET frame in the STS-12c/3c/1 bit-serial stream. In the transmit direction, the S/UNI-622 inserts these bytes into the outgoing stream either automatically or using the TTOH[4:1] inputs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 209 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) The A1 and A2 bytes are not scrambled by the frame synchronous SONET scrambler. In the receive direction when configured for STS-1 bit-serial operation, the S/UNI-622 searches for the A1, A2 bit sequence in the incoming stream to find the SONET frame boundary. When configured for STS-1, STS-3c (STM-1), or STS-12c (STM-4c) byte-serial operation, the S/UNI-622 relies on an upstream pre-framer to determine the byte alignment by finding the A1, A2 bit sequence in the SONET bit stream. Given the byte alignment, the S/UNI-622 verifies the SONET frame boundary. For all modes, the received A1 and A2 bytes are output on RTOH[4:1]. C1: The C1 bytes are currently defined as the STS-1 identification bytes for SONET and as the section trace message byte for SDH. For either case, C1 is not scrambled by the frame synchronous scrambler. In the transmit direction for an STS-N signal, the S/UNI-622 inserts the sequence 0x01,. . . 0xN for SONET applications and the value programmed in the S/UNI-622 Transmit C1 register for SDH applications. Pattern selection can be made using the S/UNI-622 Master Configuration register. For the first C1 byte, the S/UNI-622 can optionally overwrite the selected pattern with the section trace message. Internal insertion of all C1 bytes can be overridden by patterns applied to inputs TTOH[4:1]. In the receive direction, C1 bytes are output on RTOH[4:1]. In addition, the first C1 byte can be accumulated in the SSTB RAM. B1: The section bit interleaved parity byte provides a section error monitoring function. In the transmit direction, the S/UNI-622 calculates the B1 byte over all bits of the previous frame after scrambling. The calculated code is then placed in the current frame before scrambling. B1 bit errors can be induced using the TTOH[4:1] inputs. In the receive direction, the S/UNI-622 calculates the B1 code over the current SONET frame and compares this calculation with the B1 byte received in the following frame. Receive B1 errors are accumulated in an error event counter. The received B1 code is output on RTOH[4:1]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 210 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) H1, H2: The pointer value bytes locate the start of the synchronous payload envelope (SPE) in the SONET/SDH frame. In the transmit direction, the S/UNI-622 inserts a fixed pointer value, with a normal new data flag indication in the first H1-H2 pair. The concatenation indication is inserted in the remaining H1-H2 pairs. Pointer movements can be induced using the TPOP registers. H1 and H2 bit errors can be induced using the TTOH[4:1] inputs. In the receive direction, the pointer is interpreted to locate the SPE. The loss of pointer state is entered when a valid pointer cannot be found. Path AIS is detected when H1 and H2 contain all ones patterns. The received H1 and H2 codes are output on RTOH[4:1]. H3: The pointer action bytes contain synchronous payload envelope data when a negative stuff event occurs. The all zeros pattern is inserted in the transmit direction. This byte is ignored in the receive direction unless a negative stuff event is detected. B2: The line bit interleaved parity bytes provide a line error monitoring function. In the transmit direction, the S/UNI-622 calculates the B2 bytes over the line overhead bits and the entire SPE before scrambling. The calculated code is then placed in the current frame. B2 bit errors can be induced using the TTOH[4:1] inputs. In the receive direction, the S/UNI-622 calculates the B2 code over the current SONET frame and compares this calculation with the B2 code received in the following frame. Receive B2 errors are accumulated in an error event counter. The received B2 code is output on RTOH[4:1]. K2: The K2 byte is used to identify line layer maintenance signals. Line RDI is indicated when bits 6, 7 and 8 of the K2 byte are set to the pattern '110'. Line AIS is indicated when bits 6, 7 and 8 of the K2 byte are set to the pattern '111' and the entire SPE is set to an all ones pattern. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 211 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) In the transmit direction, the S/UNI-622 provides inputs TLAIS and TLRDI and internal register bits to control assertion and removal of Line AIS and Line RDI. In addition, the K2 byte can be asserted using the TTOH[4:1] inputs or the TLOP Transmit K2 register. Line AIS and Line RDI insertion has higher precedence than K2 byte assertion via inputs, TTOH[4:1] which in turn has higher precedence than insertion using the TLOP Transmit K2 register. In the receive direction, the S/UNI-622 examines the K2 byte to determine the presence of the line AIS, or the line RDI maintenance signals. In addition, the K2 byte is captured into the S/UNI-622 Receive K2 register and is also output on RTOP[4:1]. Z2: The growth byte provides a line far end block error function for remote performance monitoring. When configured for STS-1 mode, the first and only Z2 byte is used. When configured for STS-3c (STM-1) or STS-12c (STM-4c) mode, the third Z2 byte is used. In the transmit direction, the S/UNI-622 allows the Z2 byte to be sourced from the TTOH[4:1] inputs or to be internally generated. When internal generation is enabled, the number of B2 errors detected in the previous interval is inserted. This number has 9 (0 to 8), 25 (0 to 24) or 97 (0 to 96) legal values depending on the selected operating mode. In the receive direction, a legal Z2 byte value is added to the line FEBE event counter. In addition, the received Z2 bytes are output on RTOH[4:1]. Path Overhead Bytes J1: The Path Trace byte is used to repetitively transmit a 64-byte or 16-byte, fixedlength string. When not used, this byte should be set to 64 NULL characters. NULL is defined by the ASCII code, 0x00. On the transmit side, characters can be transmitted using either the TPOH input , the TPOP Path Trace register or the SPTB block. The register is the default selection and resets to 0x00 to facilitate transmission of NULL characters following reset. On the receive side, the J1 byte is brought out serially via the RPOH output and is accumulated in the SPTB RAM. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 212 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) B3: The path bit interleaved parity byte provides a path error monitoring function. In the transmit direction, the S/UNI-622 calculates the B3 bytes over all bits of the SPE capacity (including the fixed bytes if configured). The calculated code is then placed in the current frame. B3 bit errors can be induced using the TPOH inputs. In the receive direction, the S/UNI-622 calculates the B3 code over all the bits of the SPE capacity (including the fixed bytes if configured) and compares this calculation with the B3 byte received in the following frame. Receive B3 errors are accumulated in an error event counter. The received B3 code is output on RPOH. C2: The path signal label indicator identifies the SPE mapping. For ATM mappings, the identification code is 0x13. On the transmit side, the S/UNI-622 inserts this code using the TPOP Path Signal Label register or the TPOH input. On reset, the register resets to 0x13 and is the default source. On the receive side, the received code is made available in the RPOP Path Signal Label register and is output on RPOH. In addition, the SPTB block also provides circuits to detect unstable Path Signal Labels. G1: The path status byte provides a path far end block error (path FEBE) function, and provides control over the path remote defect indication signal. In the transmit direction, the S/UNI-622 provides the TPRDI input and a register bit to assert the path remote defect indication. For path FEBE, the number of B3 errors detected in the previous interval is inserted either automatically or using a register. This path FEBE code has 9 legal values, namely 0 to 8 errors. In addition, the entire G1 byte can be inserted using the TPOH input. Insertion using the TPOH input has the highest precedence. In the receive direction, a legal path FEBE value is added to the path FEBE event counter. In addition, the path remote defect indication is detected and the entire G1 byte is output on RPOH. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 213 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Cell Data Structure ATM cells may be passed to/from the S/UNI-622 using the twenty-seven word data structure shown in Figure 20: Figure 20 -16- bit Wide, 27-Word Structure Bit 15 Bit 8 H1 H3 H5 PAYLOAD1 PAYLOAD3 PAYLOAD5 Bit 7 H2 H4 HCS STATUS/CONTROL Bit 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 PAYLOAD2 PAYLOAD4 PAYLOAD6 Word 27 PAYLOAD47 PAYLOAD48 Twenty-seven 16-bit words are contained in this data structure. Bit 15 of each word is the most significant bit (which corresponds to the first bit transmitted or received). The header check sequence octet (HCS) is passed through this structure. The start of cell indication input and output (TSOC and RSOC) are coincident with Word 1 (containing the first two header octets). Word 3 of this structure contains the HCS octet in bits 15 to 8. In the receive direction, the lower 8 bits of Word 3 contain the HCS status octet. An all zeros pattern in these 8 bits indicates that the associated header is error free. An all ones pattern indicates that the header contains an uncorrectable error (if the HCSPASS bit in the RACP Control Register is set to logic zero, the all PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 214 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) ones pattern will never be passed in this structure). An alternating ones and zeros pattern (0xAA) indicates that the header contained a correctable error. In this case the header passed through the structure is the "corrected" header. In the transmit direction, the HCS bit in the TACP Control Register determines whether the HCS is calculated internally, or is inserted directly from the upper 8 bits of Word 3. The lower 8 bits of Word 3 contain the HCS control octet. The HCS control octet is an error mask that allows the insertion of one or more errors in the HCS octet. A logic one in a given bit position causes the inversion of the corresponding HCS bit position (for example a logic one in bit 7 causes the most significant bit of the HCS to be inverted). Bit Error Rate Monitor The S/UNI-622 Bit Error Rate Monitor (BERM) block counts line BIP errors over programmable periods of time and monitors whether the accumulated count of line BIP errors exceeds a programmable threshold within that specific period. The BERM block can be used to monitor the bit error rate (BER) of the line. The following tables list the recommended contents of the BERM Line BIP Accumulation Period and BERM Line BIP Threshold Period registers to detect various BERs. In STS-1 mode, the following register contents are recommended: Table 13 BER 10-4 10-5 10-6 Accumulation Period LSB 0x87 0x19 0xFA Accumulation Period MSB 0x01 0x0F 0x9C Threshold LSB 0xCA 0xD9 0xDB Threshold MSB 0x00 0x00 0x00 In STS-3c mode, the following register contents are recommended: Table 14 BER 10-4 10-5 Accumulation Period LSB 0x85 0x08 Accumulation Period MSB 0x00 0x05 Threshold LSB 0xCA 0xD9 Threshold MSB 0x00 0x00 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 215 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) BER 10-6 Accumulation Period LSB 0x53 Accumulation Period MSB 0x34 Threshold LSB 0xDB Threshold MSB 0x00 In STS-12c mode, the following register contents are recommended: Table 15 BER 10-4 10-5 10-6 10-7 JTAG Support The S/UNI-622 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below. Accumulation Period LSB 0x21 0x44 0x99 0xD0 Accumulation Period MSB 0x00 0x01 0x0D 0x82 Threshold LSB 0xCA 0xD9 0xDB 0xDB Threshold MSB 0x00 0x00 0x00 0x00 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 216 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 21 - Boundary Scan Architecture TDI Boundary Scan Register Device Identification Register Bypass Register Instruction Register and Decode Mux DFF TDO TMS Test Access Port Controller Control Select Tri-state Enable TRSTB TCK The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 217 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs. TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 218 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 22 - TAP Controller Finite State Machine TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 0 1 Exit1-IR 0 Pause-IR 1 0 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 0 1 1 Select-IR-Scan 0 1 All transitions dependent on input TMS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 219 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 220 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. Boundary Scan Instructions The following is an description of the standard instructions. Each instruction selects an serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 221 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 222 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 13 13.1 FUNCTIONAL TIMING Line Side Receive Interface Figure 23 - In Frame Declaration **** **** FPOS = '0' FPOS = '1' **** **** A1 A2 A2 A2 C1 C1 C1 1 PIN[7:0] PICLK FPIN FPIN A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 1 OOF 125 s between framing pattern occurrences **** The In Frame Declaration Timing Diagram (Figure 23) illustrates the declaration of the in-frame state by the S/UNI-622 when processing a 77.76-Mbyte/s STS-12c (STM-4c) stream on PIN[7:0]. An upstream serial-to-parallel converter indicates the location of the SONET frame using the FPIN input. The byte position marked by FPIN may be controlled using the FPOS input as illustrated in timing diagram. The frame verification is initialized by a pulse on FPIN while the S/UNI-622 is out of frame. The in-frame state is declared if the framing pattern is observed in the correct byte positions in the following frame, and in the intervening period (125 s) no additional pulses were present on FPIN. The S/UNI-622 ignores pulses on FPIN while in frame. This algorithm results in a maximum average reframe time of 250 s in the absence of mimic framing patterns. A diagram for a STS-3c (STM-1) interface would be the same as illustrated above. As selected by the FPOS input, the FPIN would identify either the third A2 byte or the byte after the C1 bytes on the PIN[7:0] input bus. However, the diagram for a STS-1 byte-serial interface would differ in that the FPIN input always identifies the byte after the C1 byte when configured for STS-1 byte-serial operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 223 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 24 PIN[7:0] PICLK OOF - Out of Frame Declaration A1 A1 A1 A2 A2 A2 A1 A1 A1 A2 A2 A2 **** **** **** **** **** A1 A1 A1 A2 A2 A2 **** A1 A1 A1 A2 A2 A2 C1 C1 C1 A1/A2 Error **** **** A1/A2 Error A1/A2 Error **** **** A1/A2 Error Four consecutive frames containing framing pattern errors The Out of Frame Declaration Timing Diagram (Figure 24) illustrates the declaration of out of frame for a STS-3c stream. In an STS-1 stream, the framing pattern is a 16-bit pattern that repeats once per frame. In an STS-3c (STM-1) stream, the framing pattern is a 48-bit pattern that repeats once per frame. In an STS-12c stream, the framing pattern is a 196-bit pattern that repeats once per frame. For the purposes of OOF declaration, the framing pattern may be modified using the ALGO2 bit in the RSOP Control Register. Out of frame is declared when one or more errors are detected in this pattern for four consecutive frames as illustrated. In the presence of random data, out of frame will normally be declared within 500 s. Figure 25 PICLK LOS - Loss of Signal Declaration/Removal **** **** **** 20 2.5 s **** **** **** **** **** Two valid framing patterns (125 s) The Loss of Signal Declaration/Removal Timing Diagram (Figure 25) illustrates the operation of the LOS output. LOS is declared when a violating period of all zeros (20 2.5 s) is observed on PIN[7:0]. LOS is removed when two valid framing patterns are observed, and in the intervening period (125 s), no violating periods of all zeros is observed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 224 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 26 PICLK OOF LOF - Loss of Frame Declaration/Removal **** **** **** **** 3 ms **** **** **** **** **** **** **** 3 ms The Loss of Frame Declaration/Removal Timing Diagram (Figure 26) illustrates the operation of the LOF output. LOF is an integrated version of OOF. LOF is declared when an out-of-frame condition persists for 3 ms. LOF is removed when an in frame condition persists for 3 ms. Figure 27 PIN[7:0] PICLK LAIS LRDI - Line AIS and Line RDI Declaration/Removal K2 **** C1 C1 **** **** **** 375 s (3 frames) or 625 s (5 frames) **** **** **** **** K2 **** C1 C1 **** **** **** 375 s (3 frames) or 625 s (5 frames) The Line AIS and Line RDI Declaration/Removal Timing Diagram (Figure 27) illustrates the operation of the LAIS and LRDI outputs. LAIS (LRDI) is declared when the binary pattern '111' ('110') is observed in bits 6,7 and 8 of the K2 byte for three or five consecutive frames as programmed using the RLOP Control/Status register. LAIS (LRDI) is removed when any pattern other than the binary pattern '111' ('110') is observed in bits 6,7 and 8 of the K2 byte for three or five consecutive frames as programmed using the RLOP Control/Status register. LAIS and LRDI may be declared or removed once per frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 225 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 28 PIN[7:0] PICLK LOP - Loss of Pointer Declaration/Removal **** **** **** **** 1ms (8 frames) **** H1 H1 **** **** **** H1 H2 H2 H2 H1 H1 H1 H2 H2 H2 **** **** **** **** 375 s (3 frames) The Loss of Pointer Declaration/Removal Timing Diagram (Figure 28) illustrates the operation of the LOP output. LOP is declared when a valid pointer cannot be determined (according to the pointer interpretation rules contained in the references) for eight consecutive frames. LOP is removed as soon as a valid pointer is determined. Figure 29 PIN[7:0] PICLK PAIS - Path AIS Declaration/Removal **** **** **** **** 375 s (3 frames) **** H1 H1 H1 H2 H2 H2 **** **** **** **** **** **** **** 375 s (3 frames) H1 H1 H1 H2 H2 H2 The Path AIS Declaration/Removal Timing Diagram (Figure 29) illustrates the operation of the PAIS output. PAIS is declared when an all-ones pattern is detected in the pointer value bytes (H1, H2) for three consecutive frames. PAIS is removed as soon as a valid pointer is determined. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 226 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 30 PIN[7:0] PICLK PRDI - Path Remote Defect Indication Declaration/Removal G1 **** **** **** **** **** **** **** G1 **** **** **** **** 1.25 ms (5 or 10 frames) **** 1.25 ms (5 or 10 frames) The Path Remote Defect Indication Declaration/Removal Timing Diagram (Figure 30) illustrates the operation of the PRDI output. RDI-P is declared when the remote defect indication bit position in the path status byte (G1) is set to logic one for five (or ten) consecutive frames. RDI-P is removed when the remote defect indication bit position is set to logic zero for five (or ten) consecutive frames. 13.2 Line Side Transmit Interface Figure 31 TSICLK GTOCLK/TCLK - STS-1 Bit-Serial Transmit Frame Alignment FPOUT POUT[7:0] A1 (F6H) A2 (28H) C1 (01H) TSOUT A1 SCRAMBLED STS-1 FRAME DATA A2 C1 The STS-1 Bit-Serial Transmit Frame alignment timing diagram (Figure 31) illustrates STS-1 bit-serial operation. The STS-1 transmit clock, TSICLK, is divided by eight to produce the byte-serial transmit clock, GTOCLK. In this application, GTOCLK is connected directly to TCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 227 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 32 POUT[7:0] TFP GTOCLK TCLK - STS-12c Byte-Serial Transmit Frame Alignment **** **** **** **** A1 **** **** **** **** A2 **** **** **** **** **** C1 nominally 81 TCLK Periods FPOUT **** **** The STS-12c Byte-Serial Transmit Frame Alignment Timing Diagram (Figure 32) illustrates the alignment of the STS-12c byte-serial transmit stream to the outgoing frame position marker (FPOUT). Input TFP is used to align the transport overhead in the transmit stream. The offset between the TFP alignment input, and the FPOUT alignment marker is nominally 81 clock periods. TFP is sampled by an internally generated version of GTOCLK that is advanced in phase relative to GTOCLK. The nominal delay is 81 TCLK cycles between the sampling of TFP and the generation of FPOUT. TFP is shown as a dotted pulse because it is not necessary for TFP to be asserted on every frame. Figure 33 POUT[7:0] TFP GTOCLK TCLK - STS-3c/1 Byte-Serial Transmit Frame Alignment **** **** **** **** A1 **** **** **** **** A2 **** **** **** **** C1 n TCLK Periods FPOUT **** **** **** PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 228 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) The STS-3c/1 Byte-Serial Transmit Frame Alignment Timing Diagram (Figure 33) illustrates the alignment of the STS-3c/1 byte-serial transmit stream to the outgoing frame position marker (FPOUT). Input TFP is used to align the transport overhead in the transmit stream. The offset between the TFP alignment input, and the FPOUT alignment marker is n where n = 18 or 26 TCLK periods when configured for STS-1 or STS-3c (STM-1) operation, respectively. TFP is shown as a dotted pulse because it is not necessary for TFP to be asserted on every frame. 13.3 Overhead Access Figure 34 RTOHFP A1 byte A1 byte A1 byte A2 byte A2 byte - Transport Overhead Extraction **** **** **** E2 byte E2 byte RTOHCLK RTOHFP A1 byte RTOHCLK A1 byte RTOH[4:1] B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 The Transport Overhead Extraction timing diagram (Figure 34) illustrates the transport overhead extraction interface. The transport overhead extraction clock, RTOHCLK is nominally a 5.184 MHz (1.728 MHz for an STS-1 stream) clock and is derived from the receive line clock, PICLK. The entire 9 row by 36, 9 or 3 column transport overhead structure is extracted and serialized on RTOH[4:1] over a frame period (125 s). When configured for STS-12 (STM-4c) operation, RTOH[1] contains the transport overhead bytes in columns 1, 5, 9, . . 33. RTOH[2] contains the transport overhead bytes in columns 2, 6, 10, . . 34. RTOH[3] contains the transport overhead bytes in columns 3, 7, 11, . . 35. RTOH[4] contains the transport overhead bytes in columns 4, 8, 12, . . 36. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 229 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) When configured for STS-3c (STM-1) or STS-1 operation, RTOH[1] contains all the transport overhead bytes. Figure 35 - Transport Overhead Orderwire and User Channel Extraction PICLK OHFP ROWCLK RSOW RLOW RSUC B1 B2 B3 B4 E1, F1, E2 B5 B6 B7 B8 approx 750 ns OHFP ROWCLK The Transport Overhead Orderwire and User Channel Extraction diagram (Figure 35) shows the relationship between the RSOW, RSUC and RLOW serial data outputs and their associated clock, ROWCLK. ROWCLK is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate and is aligned as shown in the timing diagram. The E1, F1 and E2 bytes shifted out of the S/UNI-622 on RSOW, RSUC and RLOW in the frame shown are extracted from the corresponding transport overhead channels in the previous frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 230 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 36 FPIN - Transport Overhead Data Link Clock and Data Extraction Row 1 bytes Row 2 bytes Row 3 bytes Row 4 bytes Row 5 bytes Row 6 bytes Row 7 bytes Row 8 bytes Row 9 bytes RSDCLK RSD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 approx. 2 MHz DLCLK bursts RLDCLK RLD RLDCLK RLD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 The Transport Overhead Data Link Clock and Data Extraction timing diagram (Figure 36) shows the relationship between the RSD and RLD serial data outputs, and their associated clocks, RSDCLK and RLDCLK. RSDCLK is a 216 kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate that is aligned with FPIN as shown in the timing diagram. RLDCLK is a 2.16 MHz, 67%/33% (high/low) duty cycle clock that is gapped to produce a 576 kHz nominal rate that is aligned with FPIN as shown in the timing diagram. RSD (RLD) is updated on the falling RSDCLK (RLDCLK) edge. The D1-D3 and D4-D12 bytes shifted out of the S/UNI-622 in the frame shown are extracted from the corresponding receive line overhead channels in the previous frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 231 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 37 RPOHFP - Path Overhead Extraction **** J1 byte B3 byte C2 byte G1 byte F2 byte **** **** Z4 byte Z5 byte RPOHCLK J1 byte RPOHCLK RPOHFP RPOH B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B3 byte B2 B3 B4 B5 B6 B7 B8 B1 The Path Overhead Extraction Timing Diagram (Figure 37) illustrates the path overhead extraction interface. The path overhead extraction clock, RPOHCLK, is nominally a 576 kHz clock and is derived from the receive line clock, PICLK. The entire path overhead (the complete 9-byte structure) is extracted, serialized and output on RPOH over a frame time. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 232 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 38 TTOHFP - Transport Overhead Insertion **** A1 byte A1 byte A1 byte A2 byte A2 byte **** **** E2 byte E2 byte TTOHCLK A1 byte TTOHCLK TTOHFP TTOH[4:1] TTOHEN A1 byte B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 The transport overhead insertion timing diagram (Figure 38) illustrates the transport overhead insertion interface. Output TTOHCLK is nominally a 5.184 MHz clock (1.728 MHz for an STS-1 stream) and is used to update output TTOHFP and to sample inputs TTOH[4:1] and TTOHEN. The value sampled on , TTOHEN during the first overhead bit position of a given set of overhead bytes determines whether the values sampled on TTOH[4:1] are inserted in the STS-12c/3c/1 stream. In Figure 38, the STS-12c (STM-4c) case is shown. TTOHEN is held high during the position of bit 1 of the first group of four A1 bytes in the TTOH[4:1] stream. The eight bits sampled on input TTOH[4:1] during the first A1 byte period are inserted in the first through fourth A1 byte positions in the STS-12c stream. Similarly, TTOHEN is held low during the bit 1 position of the second group of four A1 bytes. The default value (F6H) is inserted in the fifth through eighth A1 byte positions in the STS-12c stream. For the STS-3c (STM-1) and STS-1 cases, only input TTOH[1] is used. An error insertion feature is also provided for the B1, H1, H2, and B2 byte positions. When TTOH[4:1] is held high during any of the bit positions corresponding to these bytes, the corresponding bit is inverted before being PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 233 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) inserted in the STS-12c/3c/1 stream (TTOHEN must be sampled high during the first bit position to enable the error insertion mask). Figure 39 - Transport Overhead Orderwire and User Channel Insertion TCLK FPOUT TOWCLK TSOW TSUC TLOW B1 B2 B3 B4 E1, F1, E2 B5 B6 B7 B8 approx 750 ns FPOUT TOWCLK The Transport Overhead Orderwire and User Channel Insertion diagram (Figure 39) shows the relationship between the TSOW, TLOW and TSUC serial data inputs and their associated clock TOWCLK. TOWCLK is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate and is aligned as shown in the timing diagram. The E1, E2 and F1 bytes shifted into the S/UNI-622 on TSOW, TLOW and TSUC in the frame shown are inserted in the corresponding transport overhead channels in the next frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 234 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 40 FPOUT - Transport Overhead Data Link Clock and Data Insertion Row 1 bytes TSDCLK TSD B1 Row 2 bytes Row 3 bytes Row 4 bytes Row 5 bytes Row 6 bytes Row 7 bytes Row 8 bytes Row 9 bytes B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 approx. 2 MHz DLCLK bursts TLDCLK TLD TLDCLK TLD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 The Transport Overhead Data Link Clock and Data Insertion timing diagram (Figure 40) shows the relationship between the TSD and TLD serial data inputs, and their associated clocks TSDCLK and TLDCLK respectively. TSDCLK is a 216 kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate that is aligned with FPOUT as shown in the timing diagram. TLDCLK is a 2.16 MHz 67%/33% (high/low) duty cycle clock that is gapped to produce a 576 kHz nominal rate that is aligned with FPOUT as shown in the timing diagram. TSD (TLD) is sampled on the rising TSDCLK (TLDCLK) edge. The D1D3, and D4-D12 bytes shifted into the S/UNI-622 in the frame shown are inserted in the corresponding transport overhead channels in the following frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 235 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 41 TPOHFP - Path Overhead Insertion **** J1 byte B3 byte C2 byte G1 byte F2 byte **** **** Z4 byte Z5 byte TPOHCLK J1 byte TPOHCLK TPOHFP TPOH TPOHEN B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B3 byte B2 B3 B4 B5 B6 B7 B8 B1 The Path Overhead Insertion Timing Diagram (Figure 41) illustrates the path overhead insertion interface. Output TPOHCLK is nominally a 576 kHz clock, and is used to update output TPOHFP and to sample inputs TPOH and , TPOHEN. In Figure 41, TPOHEN is held high throughout the eight bit positions of the J1 byte. The eight bits sampled on input TPOH are inserted in the J1 byte position in the STS-12c/3c/1 stream. If TPOHEN was low during any of the eight bit locations, the internally generated bit values of the corresponding bit positions would be inserted in the J1 byte. For the B3 and H4 byte positions, an error insertion feature is provided. TPOHEN is held high during bit positions 2, 5, 6, 7 and 8 of the B3 byte. The values sampled on input TPOH are used as an error mask in the corresponding bit positions (2, 5, 6, 7 and 8) of the B3 byte in the STS-12c/3c/1 stream. If TPOH and TPOHEN are high during a bit location, the corresponding bit of the internally generated B3 byte is inverted before transmission. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 236 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 13.4 GFC Access Figure 42 - GFC Extraction Port SPECLK RGFCE[3:0]=1111B RCP RGFC GFC[3] CELL N GFC[2] CELL N GFC[1] CELL N GFC[0] CELL N RGFCE[3:0]=1010B RCP RGFC GFC[3] CELL N GFC[1] CELL N The GFC Control Port Diagram (Figure 42) illustrates the operation of the receive generic flow control, RGFC, and receive GFC control pulse, RCP outputs. The , first RGFC bit position, which is coincident with the RCP being high, contains the first GFC bit received and corresponds to the first bit of the cell. Extraction of the GFC[3:0] bits is controlled by the four RGFC enable (RGFCE[3:0]) bits in the RACP GFC Control register. The output value in each GFC bit postition can be forced low by setting the corresponding RGFCE bit to zero. The serial link is inactive (forced low) if the S/UNI-622 is out of cell delineation or if the current cell contains an uncorrected header. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 237 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 43 GTOCLK TCP TGFC X - GFC Insertion Port GFC[3] CELL N GFC[2] CELL N GFC[1] CELL N GFC[0] CELL N X The GFC Insertion Port Diagram (Figure 43) illustrates the relationship between the transmit cell pulse, TCP output and the transmit generic flow control, TGFC input. The MSB (GFC[3]) of the four-bit GFC code on the TGFC input is identified using the TCP output. The S/UNI-622 accumulates the code and transmits the code in the next transmit cell. If the next transmit cell is an idle/unassigned cell, the GFC code provided in the Idle/Unassigned Cell Header Pattern register is overwritten. If the next transmit cell was read from the FIFO, the GFC code passed through the FIFO is overwritten. 13.5 Drop Side Receive Interface Figure 44 - Receive Synchronous FIFO, TSEN=0, RCALEVEL0=1 RFCLK RRDENB RSOC RCA RDAT[15:0] RXPRTY[1:0] XX XX W1 W2 **** **** **** **** **** **** W(n-2) W(n-1) XX W(n) XX invalid read, no data available XX W(1) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 238 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 45 - Receive Synchronous FIFO, TSEN=0, RCALEVEL0=0 RFCLK RRDENB RCA RDAT[15:0] RXPRTY[1:0] XX XX W1 W2 **** **** **** **** **** W(n-5) W(n-4) W(n-3) W(n-2) W(n-1) W(n) W(1) The receive synchronous FIFO is controlled by the ATM Layer device using the RRDENB signal. All signals must be updated and sampled using the rising edge of the receive FIFO clock, RFCLK. The PHY layer device indicates that a cell is available by asserting the receive cell available signal, RCA. RCA remains high until the internal FIFO of the PHY layer device is near empty or empty. Near empty implies that the ATM Layer device can initiate at most four additional reads. The selection of the empty or near empty operating modes is made by the RCALEVEL0 bit in register 0x52. The ATM Layer device indicates, by asserting the RRDENB signal, that the data on the RDAT bus during the next RFCLK cycle will be read from the PHY layer device. Figure 44 illustrates the empty operating mode. RCA transitions low when the last word of the last cell is available on the RDAT bus. The RDAT bus, RXPRTY and RSOC are valid in cycles for which RCA is high and RRDENB was low is the previous cycle. If the ATM Layer device requests a read while RCA is deasserted, the PHY layer device will ignore the additional reads. Figure 45 illustrates the near empty operating mode. RCA transitions low four words before the last word of the last cell is read from the PHY layer device. RCA remains low for a minimum of one RFCLK clock cycle and then can transition high to indicate that there are additional cells available from the PHY layer device. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 239 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Once RCA is deasserted and has been sampled, the ATM Layer device can issue no more than four reads. If the ATM Layer device issues more reads than the allowable number, and RCA remains deasserted throughout, the PHY layer device will ignore the additional reads. Figure 46 - Receive Synchronous FIFO, TSEN=1, RCALEVEL0=1 RFCLK RRDENB RSOC RCA RDAT[15:0] RXPRTY[1:0] W1 W2 **** **** **** **** **** **** W(n-2) W(n-1) W(n) XX invalid read, no data available W(1) The Receive Synchronous FIFO Timing, TSEN=1, RCALEVEL0=1 Diagram (Figure 46) illustrates the operation of the drop side receive interface with tristating enabled. Figure 46 is similar to figure Figure 44 except that outputs RSOC, RDAT[15:0] and RXPRTY[1:0] are tristated in the clock cycle following the removal of RRDENB. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 240 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 13.6 Drop Side Transmit Interface Figure 47 - Transmit Synchronous FIFO **** **** **** XX XX W1 W2 XX W3 TFCLK TCA TWRENB TDAT[15:0] **** **** **** W(n-4) W(n-3) W(n-2) W(n-1) W(n) W1 TXPRTY[1:0] TSOC The S/UNI-622 transmit interface is controlled by the ATM Layer device using the TWRENB signal. All signals must be updated and sampled using the rising edge of the transmit FIFO clock, TFCLK. As shown in Figure 47, the S/ UNI-622 layer device indicates that there is space available for a full cell in its internal FIFO by asserting the transmit cell available signal, TCA. TCA remains asserted until the transmit FIFO is almost full or full. Almost full implies that the S/UNI-622 can accept at most an additional four writes after the current write (TCALEVEL0 is logic 0) while full implies that the S/UNI-622 can accept no additional writes after the completion of the current write (TCALEVEL0 is logic 1). The TCALEVEL0 bit is contained in register 0x63 If TCA is asserted and the ATM Layer device is ready to write a word, it should assert TWRENB low and present the word on the TDAT bus. If the presented word is the first word of a cell, the ATM Layer device should also assert signal TSOC. At any time, if the ATM Layer device does not have a word to write, it can deassert TWRENB. When TCA is deasserted and it has been sampled, the ATM Layer device can write no more than four bytes or words to the PHY layer device. If the ATM Layer writes more than four words and TCA remains deasserted throughout, the PHY layer device will indicate an error condition and ignore additional writes until it asserts TCA again. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 241 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 14 ABSOLUTE MAXIMUM RATINGS Table 16 - Absolute Maximum Ratings -40C to +85C -40C to +125C -0.5V to +6.0V -0.5V to V DD+0.5V 500 V 100 mA 20 mA +230C +150C Case Temperature under Bias Storage Temperature Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 242 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 15 D.C. CHARACTERISTICS TC = -40C to +85C, VDD = 5 V 5% (Typical Conditions: TC = 25C, VDD = 5 V) Table 17 Symbol VDD VIL Parameter Power Supply Input Low Voltage (TTL Only) Min 4.75 -0.5 Typ 5 1.4 Max 5.25 0.8 Units Volts Volts Guaranteed Input LOW Voltage Conditions VIH Input High Voltage (TTL Only) 2.0 1.4 VDD +0.5 Volts Guaranteed Input HIGH Voltage VOL Output or Bidirectional Low Voltage (TTL Only) 0.1 0.4 Volts VDD = min, IOL = -4 mA for D[7:0], POUT[7:0], FPOUT, TSOUT, GTOCLK, GROCLK, TCA, RDAT[15:0], RXPRTY[1:0], RCA and RSOC, and -2 mA for all other outputs. Note 3 VOH Output or Bidirectional High Voltage (TTL Only) 2.4 4.7 Volts VDD = min, IOH = 4 mA for D[7:0], POUT[7:0], FPOUT, TSOUT, GTOCLK, GROCLK, TCA, RDAT[15:0], RXPRTY[1:0], RCA and RSOC, and 2 mA for all other outputs. Note 3 VT+ Reset Input High Voltage 3.5 Volts VT- Reset Input Low Voltage 0.6 Volts VTH Reset Input Hysteresis Voltage 1.0 Volts IILPU IIHPU IIL IIH CIN Input Low Current Input High Current Input Low Current Input High Current Input Capacitance +175 -10 -10 -10 +350 0 0 0 5 +525 +10 +10 +10 A A A A pF VIL = GND. Notes 1, 3 VIH = VDD. Notes 1, 3 VIL = GND. Notes 2, 3 VIH = VDD. Notes 2, 3 Excluding Package, Package Typically 2 pF PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 243 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Symbol COUT Parameter Output Capacitance Min Typ 5 Max Units pF Conditions Excluding Package, Package Typically 2 pF CIO Bidirectional Capacitance 5 pF Excluding Package, Package Typically 2 pF IDDOP1s Operating Current Processing Cells 60 90 mA VDD = 5.25 V, Outputs Unloaded, RSICLK = 51.84 MHz TSICLK = 51.84 MHz RFCLK = 52 MHz TFCLK = 52 MHz IDDOP1 Operating Current Processing Cells Note 4 mA VDD = 5.25 V, Outputs Unloaded, PICLK = 6.48 MHz TCLK = 6.48 MHz RFCLK = 52 MHz TFCLK = 52 MHz IDDOP3c Operating Current Processing Cells Note 4 mA VDD = 5.25 V, Outputs Unloaded, PICLK = 19.44 MHz TCLK = 19.44 MHz RFCLK = 52 MHz TFCLK = 52 MHz IDDOP12c Operating Current Processing Cells 210 270 mA VDD = 5.25 V, Outputs Unloaded, PICLK = 77.76 MHz TCLK = 77.76 MHz RFCLK = 52 MHz TFCLK = 52 MHz Notes on D.C. Characteristics: 1. Input pin or bidirectional pin with internal pull-up resistor. 2. Input pin or bidirectional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 244 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 4. Characterization data for IDDOP1 and IDDOP3c is not available at this time. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 245 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TC = -40C to +85C, VDD = 5 V 5%) Table 18 Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH - Microprocessor Interface Read Access (Figure 48) Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to Output Tri-state Min 10 5 10 10 20 0 5 70 20 50 Max Units ns ns ns ns ns ns ns ns ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 246 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 48 - Microprocessor Interface Read Timing tSA R A[7:0] V alid tS ALR tV L A d d re ss tH A R tH ALR ALE tS L R (C S B +R D B ) tZ IN T H IN T B tHLR tP R D D [7:0] tZ R D V alid D ata Notes on Microprocessor Interface Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point o\ the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. Microprocessor Interface timing applies to normal mode register accesses only. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 247 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 5. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable. 6. Parameter tHAR is not applicable if address latching is used. 7. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 8. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. Table 19 Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR - Microprocessor Interface Write Access (Figure 49) Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 20 10 10 20 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 248 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 49 - Microprocessor Interface Write Timing A[7:0] tS ALW tV L ALE tSAW (CSB+WRB) Valid Address tH ALW tS LW tHLW tVWR tH AW tS DW D[7:0] tH DW Valid Data Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. Microprocessor Interface timing applies to normal mode register accesses only. 3. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW, tHALW, tVL, and tSLW are not applicable. 4. Parameter tHAW is not applicable if address latching is used. 5. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 6. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 249 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 17 S/UNI-622 TIMING CHARACTERISTICS (TC = -40C to +85C, VDD = 5 V 5%) Table 20 Symbol - Line Side Receive Interface (Figure 50) Description PICLK Frequency (nominally 77.76 MHz) PICLK Duty Cycle tSPIN tHPIN tSFPIN tHFPIN PIN[7:0] Set-up time to PICLK PIN[7:0] Hold time to PICLK FPIN Set-up time to PICLK FPIN Hold time to PICLK RSICLK Frequency (nominally 51.84 MHz) RSICLK Duty Cycle tSRSIN tHRSIN tPGROCLK RSIN Set-up Time to RSICLK RSIN Hold Time to RSICLK RSICLK High to GROCLK Valid Prop Delay 33 5 2 5 30 40 3.5 1 3.5 1 52 67 Min Max 78 60 Units MHz % ns ns ns ns MHz % ns ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 250 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 50 - Line Side Receive Interface Timing PICLK tS PIN PIN[7:0] tS FPIN FPIN tH FPIN tH PIN RSICLK tS RSIN RSIN tP GROCLK GROCLK tH RSIN Table 21 Symbol tPGROCLK tPOOF tPLOF tPLOS - Receive Alarm Output (Figure 51) Description PICLK High to GROCLK Edge PICLK High to OOF Valid PICLK High to LOF Valid PICLK High to LOS Valid Min 3 3 3 3 Max 25 30 30 30 Units ns ns ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 251 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Symbol tPLAIS tPLRDI tPLOP tPPAIS PPRDI tPLCD Description PICLK High to LAIS Valid PICLK High to LRDI Valid GROCLK Low to LOP Valid GROCLK Low to PAIS Valid GROCLK Low to PRDI Valid GROCLK Low to LCD Valid Min 3 3 3 3 3 3 Max 30 30 25 25 25 25 Units ns ns ns ns ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 252 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 51 - Receive Alarm Output Timing PICLK tP GROCLK GROCLK tP OOF OOF tP LOF LOF tP LOS LOS tP LAIS LAIS tP LRDI LRDI PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 253 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) GROCLK tP LOP LOP tP PAIS PAIS tP PRDI PRDI tP LCD LCD Table 22 Symbol tPRTOH tPRTOHFP tPROW tPRSD tPRLD tPRPOH tPRPOHFP - Receive Overhead Access (Figure 52) Description RTOHCLK Low to RTOH[4:1] Valid RTOHCLK Low to RTOHFP Valid ROWCLK Low to RSOW, RSUC, RLOW Valid Prop Delay RSDCLK Low to RSD Valid RLDCLK Low to RLD Valid RPOHCLK Low to RPOH Valid RPOHCLK Low to RPOHFP Valid -250 250 -15 -15 -15 -15 15 15 15 15 ns ns ns ns ns Min -15 -15 Max 15 15 Units ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 254 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 52 - Receive Overhead Access Timing RTOHCLK tP RTOH RTOH[4:1] tP RTOHFP RTOHFP RPOHCLK tP RPOH RPOH tP RPOHFP RPOHFP PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 255 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) ROWCLK tP ROW RSOW RSUC RLOW RSDCLK tP RSD RSD RLDCLK tP RLD RLD Table 23 Symbol tPRCP tPRGFC - Receive Overhead Access (Figure 53) Description GROCLK Low to RCP Valid GROCLK Low to RGFC Valid Min 3 3 Max 25 25 Units ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 256 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 53 - Receive GFC Access Timing GROCLK tP RCP RCP tP RGFC RGFC Table 24 Symbol - Line Side Transmit Interface (Figure 54) Description TCLK Frequency (nominally 77.76 MHz) TCLK Duty Cycle 40 1 1 2 Min Max 78 60 11 11 25 52 33 2 4 67 15 25 Units MHz % ns ns ns MHz % ns ns tPFPOUT tPPOUT tPGTOCLK TCLK High to FPOUT Valid TCLK High to POUT[7:0] Valid TCLK Edge to GTOCLK Edge TSICLK Frequency (nominally 51.84 MHz) TSICLK Duty Cycle tPTSOUT tPGTOCLK TSICLK High to TSOUT Valid Prop Delay TSICLK High to GTOCLK Valid Prop Delay PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 257 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 54 - Line Side Transmit Interface Timing TCLK tP POUT[7:0] tP FPOUT tP GTOCLK POUT FPOUT GTOCLK TSICLK tPTSOUT TSOUT tP GTOCLK GTOCLK Table 25 Symbol tSTLAIS tHTLAIS - Transmit Alarm Input (Figure 55) Description TLAIS Set-up time to TCLK TLAIS Hold time to TCLK Min 3 3 Max Units ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 258 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Symbol tSTLRDI tHTLRDI tSTPAIS tHTPAIS tSTPRDI tHTPRDI tSTFP tHTFP Figure 55 Description TLRDI Set-up time to TCLK TLRDI Hold time to TCLK TPAIS Set-up time to GTOCLK TPAIS Hold time to GTOCLK TPRDI Set-up time to GTOCLK TPRDI Hold time to GTOCLK TFP Set-up time to GTOCLK TFP Hold time to GTOCLK - Transmit Alarm Input Timing Min 3 3 10 5 10 5 10 5 Max Units ns ns ns ns ns ns ns ns TCLK tS TLAIS TLAIS tS TLRDI TLRDI tH TLRDI tH TLAIS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 259 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) GTOCLK tS TPAIS TPAIS tS TPRDI TPRDI tS TFP TFP tH TFP tH TPRDI tH TPAIS Table 26 Symbol tPTTOHFP tPTPOHFP tSTTOH tHTTOH tSTTOHEN tHTTOHEN tSTOW tHTOW tSTSD tHTSD - Transmit Overhead Access (Figure 56) Description TTOHCLK Low to TTOHFP Valid TPOHCLK Low to TPOHFP Valid TTOH[4:1] Set-up time to TTOHCLK TTOH[4:1] Hold time to TTOHCLK TTOHEN Set-up time to TTOHCLK TTOHEN Hold time to TTOHCLK TSOW, TSUC, TLOW Set-up Time to TOWCLK TSOW, TSUC, TLOW Hold Time to TOWCLK TSD Set-up Time to TSDCLK TSD Hold Time to TSDCLK Min -15 -15 15 5 15 5 15 10 15 10 Max 15 15 Units ns ns ns ns ns ns ns ns ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 260 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Symbol tSTLD tHTLD tSTPOH tHTPOH tSTPOHEN tHTPOHEN Figure 56 Description TLD Set-up Time to TLDCLK TLD Hold Time to TLDCLK TPOH Set-up time to TPOHCLK TPOH Hold time to TPOHCLK TPOHEN Set-up time to TPOHCLK TPOHEN Hold time to TPOHCLK - Transmit Overhead Access Timing Min 15 10 15 5 15 5 Max Units ns ns ns ns ns ns TTOHCLK tP TTOHFP TTOHFP TPOHCLK tP TPOHFP TPOHFP PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 261 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) TTOHCLK tS TTOH[4:1] tS TTOHEN TTOH tH TTOH tH TTOHEN TTOHEN TPOHCLK tS TPOH tS TPOHEN TPOH tH TPOH tH TPOHEN TPOHEN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 262 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) TOWCLK tS TSOW TSUC TLOW tH TOW TOW TSDCLK tS TSD tH TSD TSD TLDCLK tS TLD tH TLD TLD Table 27 Symbol tPTCP tSTGFC tHTGFC - Transmit GFC Access (Figure 57) Description GTOCLK Low to TCP Valid TGFC Set-up time to GTOCLK TGFC Hold time to GTOCLK Min 3 5 1 Max 20 Units ns ns ns PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 263 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 57 - Transmit GFC Access Timing GTOCLK tP TCP TCP tS TGFC tH TGFC TGFC Table 28 Symbol - Drop Side Receive Interface (Figure 58) Description RFCLK Frequency RFCLK Duty Cycle 40 4 1 2 2 2 2 2 2 14 14 14 14 14 14 Min Max 52 60 Units MHz % ns ns ns ns ns ns ns ns tSRRDENB tHRRDENB tPRCA tPRSOC tPRDAT tPRXPRTY tPRFCLK tZRFCLK RRDENB Set-up time to RFCLK RRDENB Hold time to RFCLK RFCLK High to RCA Valid RFCLK High to RSOC Valid RFCLK High to RDAT[15:0] Valid RFCLK High to RXPRTY[1:0] Valid RFCLK High to Output Enable RFCLK High to Output Tristate PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 264 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 58 - Drop Side Receive Interface Timing RFCLK tS RRDENB tH RRDENB RRDENB tP RDAT RDAT[15:0] tP RXPRTY RXPRTY[1:0] tP RCA RCA tP RSOC RSOC PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 265 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) RFCLK TSEN=1 RRDENB tPRFCLK RDAT[15:0] RXPRTY[1:0] RSOC tZRFCLK Valid Data Table 29 Symbol - Drop Side Transmit Interface (Figure 59) Description TFCLK Frequency TFCLK Duty Cycle 40 4 1 4 1 4 1 4 1 2 14 Min Max 52 60 Units MHz % ns ns ns ns ns ns ns ns ns tSTWRENB tHTWRENB tSTDAT tHTDAT tSTXPRTY tHTXPRTY tSTSOC tHTSOC tPTCA TWRENB Set-up time to TFCLK TWRENB Hold time to TFCLK TDAT[15:0] Set-up time to TFCLK TDAT[15:0] Hold time to TFCLK TXPRTY[1:0] Set-up time to TFCLK TXPRTY[1:0] Hold time to TFCLK TSOC Set-up time to TFCLK TSOC Hold time to TFCLK TFCLK High to TCA Valid PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 266 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Figure 59 - Drop Side Transmit Interface TFCLK tS TWRENB tH TWRENB TWRENB tS TDAT tH TDAT TDAT[15:0] tS tH TXPRTY TXPRTY TXPRTY[1:0] tS TSOC tH TSOC TSOC tP TCA TCA Table 30 Symbol - JTAG Port Interface (Figure 60) Description TCK Frequency TCK Duty Cycle 40 50 50 Min Max 1 60 Units MHz % ns ns tSTMS tHTMS TMS Set-up time to TCK TMS Hold time to TCK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 267 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) Symbol tSTDI tHTDI tPTDO Figure 60 Description TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid - JTAG Port Interface Timing Min 50 50 2 Max Units ns ns 50 ns TCK tS TMS TMS tS TDI TDI tH TDI tH TMS TCK tP TDO TDO Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 268 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. Notes on Output Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 50 pF load on the outputs with the exception of the POUT[7:0], FPOUT and TSOUT outputs. The POUT[7:0], FPOUT and TSOUT output propagation delays are measured with a 30 pF load. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 269 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 18 ORDERING AND THERMAL INFORMATION Table 31 PART NO. PM5355-SI Table 32 PART NO. PM5355-SI CASE TEMPERATURE -40C to 85C Theta Ja 24 C/W Theta Jc 8 C/W DESCRIPTION 208 Slugged Plastic Quad Flat Pack (PQFP) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 270 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) 19 MECHANICAL INFORMATION D D1 208 A 1 Pin 1 Designator e E E1 Hy 8-12 DEG. 8-12 DEG. EXPOSED HEATSINK Hx A2 SEE DETAIL A 0-10 DEG. STANDOFF NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE. A .25 A1 SEATING PLANE C 0-7 DEG L b C 0.13-0.23 LEAD COPLANARITY ccc C DETAIL A PACKAGE TYPE: 208 PIN SLUGGED METRIC PLASTIC QUAD FLATPACK-SMQFP BODY SIZE: 28 x 28 x 3.49 MM Dim. Min. Nom. Max. A 3.45 3.75 4.10 A1 0.25 0.35 0.43 A2 3.17 3.40 3.67 D 30.35 30.60 30.85 D1 27.80 28.00 28.20 E 30.35 30.60 30.85 E1 27.80 28.00 28.20 L 0.45 0.60 0.75 0.50 e b 0.17 0.22 0.27 0.10 21.00 21.00 ccc Hx Hy PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 271 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 272 PM5355 S/UNI-622 DATA SHEET PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb) CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PMC-941027 (R3) ref PMC-930527 (R8) Issue date: June 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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